X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=gdb%2Fxtensa-tdep.h;h=a1e7188d52330b5e5a8db42412c74e4c077d7a62;hb=e05523bd2411bac0277da73556f4d01f6c7448aa;hp=3d5390c7fac1d51bcc3e7ac287f823d72d5c0387;hpb=ca3bf3bdbe69f60b3ab1c834e621297f2fec0775;p=binutils-gdb.git
diff --git a/gdb/xtensa-tdep.h b/gdb/xtensa-tdep.h
index 3d5390c7fac..a1e7188d523 100644
--- a/gdb/xtensa-tdep.h
+++ b/gdb/xtensa-tdep.h
@@ -1,12 +1,12 @@
/* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
- Copyright (C) 2003, 2005, 2006 Free Software Foundation, Inc.
+ Copyright (C) 2003-2022 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
+ the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
@@ -15,10 +15,14 @@
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street, Fifth Floor,
- Boston, MA 02110-1301, USA. */
+ along with this program. If not, see . */
+#ifndef XTENSA_TDEP_H
+#define XTENSA_TDEP_H
+
+#include "arch/xtensa.h"
+#include "gdbarch.h"
+#include "xtensa-config.h"
/* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION
whenever the "tdep" structure changes in an incompatible way. */
@@ -44,6 +48,8 @@ typedef enum
/* Xtensa register group. */
+#define XTENSA_MAX_COPROCESSOR 0x10 /* Number of Xtensa coprocessors. */
+
typedef enum
{
xtRegisterGroupUnknown = 0,
@@ -58,6 +64,17 @@ typedef enum
xtRegisterGroupFloat = 0x0400, /* Floating Point. */
xtRegisterGroupVectra = 0x0800, /* Vectra. */
xtRegisterGroupSystem = 0x1000, /* System. */
+
+ xtRegisterGroupNCP = 0x00800000, /* Non-CP non-base opt/custom. */
+ xtRegisterGroupCP0 = 0x01000000, /* CP0. */
+ xtRegisterGroupCP1 = 0x02000000, /* CP1. */
+ xtRegisterGroupCP2 = 0x04000000, /* CP2. */
+ xtRegisterGroupCP3 = 0x08000000, /* CP3. */
+ xtRegisterGroupCP4 = 0x10000000, /* CP4. */
+ xtRegisterGroupCP5 = 0x20000000, /* CP5. */
+ xtRegisterGroupCP6 = 0x40000000, /* CP6. */
+ xtRegisterGroupCP7 = 0x80000000, /* CP7. */
+
} xtensa_register_group_t;
@@ -70,46 +87,19 @@ typedef enum
} xtensa_target_flags_t;
-/* Xtensa ELF core file register set representation ('.reg' section).
- Copied from target-side ELF header . */
-
-typedef unsigned long xtensa_elf_greg_t;
+/* Mask. */
-typedef struct
+typedef struct
{
- xtensa_elf_greg_t xchal_config_id0;
- xtensa_elf_greg_t xchal_config_id1;
- xtensa_elf_greg_t cpux;
- xtensa_elf_greg_t cpuy;
- xtensa_elf_greg_t pc;
- xtensa_elf_greg_t ps;
- xtensa_elf_greg_t exccause;
- xtensa_elf_greg_t excvaddr;
- xtensa_elf_greg_t windowbase;
- xtensa_elf_greg_t windowstart;
- xtensa_elf_greg_t lbeg;
- xtensa_elf_greg_t lend;
- xtensa_elf_greg_t lcount;
- xtensa_elf_greg_t sar;
- xtensa_elf_greg_t syscall;
- xtensa_elf_greg_t ar[0]; /* variable size (per config). */
-} xtensa_elf_gregset_t;
-
-#define SIZEOF_GREGSET (sizeof (xtensa_elf_gregset_t) + NUM_AREGS * 4)
-#define XTENSA_ELF_NGREG (SIZEOF_GREGSET / sizeof(xtensa_elf_greg_t))
-
-
-/* Mask. */
+ int reg_num;
+ int bit_start;
+ int bit_size;
+} xtensa_reg_mask_t;
typedef struct
{
int count;
- struct
- {
- int reg_num;
- int bit_start;
- int bit_size;
- } mask[0];
+ xtensa_reg_mask_t *mask;
} xtensa_mask_t;
@@ -117,7 +107,7 @@ typedef struct
typedef struct
{
- char* name; /* Register name. */
+ const char *name; /* Register name. */
int offset; /* Offset. */
xtensa_register_type_t type; /* Register type. */
xtensa_register_group_t group;/* Register group. */
@@ -129,19 +119,28 @@ typedef struct
unsigned int target_number; /* Register target number. */
int flags; /* Flags. */
+ int coprocessor; /* Coprocessor num, -1 for non-CP, else -2. */
const xtensa_mask_t *mask; /* Register is a compilation of other regs. */
const char *fetch; /* Instruction sequence to fetch register. */
const char *store; /* Instruction sequence to store register. */
} xtensa_register_t;
-
-#define XTENSA_REGISTER_FLAGS_PRIVILEDGED 0x0001
+/* For xtensa-config.c to expand to the structure above. */
+#define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \
+ {#name, ofs, (xtensa_register_type_t) (ty), \
+ ((xtensa_register_group_t) \
+ ((gr) | ((xtRegisterGroupNCP >> 2) << (cp + 2)))), \
+ ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto},
+#define XTREG_END \
+ {0, 0, (xtensa_register_type_t) 0, (xtensa_register_group_t) 0, \
+ 0, 0, 0, 0, (unsigned) -1, 0, 0, 0, 0, 0},
+
+#define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001
#define XTENSA_REGISTER_FLAGS_READABLE 0x0002
#define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004
#define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008
-
/* Call-ABI for stack frame. */
typedef enum
@@ -151,127 +150,98 @@ typedef enum
} call_abi_t;
+struct ctype_cache
+{
+ struct ctype_cache *next;
+ int size;
+ struct type *virtual_type;
+};
+
+#ifndef XCHAL_NUM_CONTEXTS
+# define XCHAL_NUM_CONTEXTS 0
+#endif
+
+#ifndef XCHAL_HAVE_EXCEPTIONS
+# define XCHAL_HAVE_EXCEPTIONS 1
+#endif
+
/* Xtensa-specific target dependencies. */
-struct gdbarch_tdep
+struct xtensa_gdbarch_tdep : gdbarch_tdep
{
- unsigned int target_flags;
+ xtensa_gdbarch_tdep (xtensa_register_t *regmap)
+ : regmap (regmap)
+ {}
+
+ unsigned int target_flags = 0;
/* Spill location for TIE register files under ocd. */
- unsigned int spill_location;
- unsigned int spill_size;
+ unsigned int spill_location = (unsigned int) -1;
+ unsigned int spill_size = 0;
+
+ char *unused = nullptr; /* Placeholder for compatibility. */
- char *unused; /* Placeholder for compatibility. */
- call_abi_t call_abi; /* Calling convention. */
+ /* Calling convention. */
+ call_abi_t call_abi = (XSHAL_ABI == XTHAL_ABI_CALL0
+ ? CallAbiCall0Only : CallAbiDefault);
/* CPU configuration. */
- unsigned int debug_interrupt_level;
+ unsigned int debug_interrupt_level = XCHAL_DEBUGLEVEL;
- unsigned int icache_line_bytes;
- unsigned int dcache_line_bytes;
- unsigned int dcache_writeback;
+ unsigned int icache_line_bytes = XCHAL_ICACHE_LINESIZE;
+ unsigned int dcache_line_bytes = XCHAL_DCACHE_LINESIZE;
+ unsigned int dcache_writeback = XCHAL_DCACHE_IS_WRITEBACK;
- unsigned int isa_use_windowed_registers;
- unsigned int isa_use_density_instructions;
- unsigned int isa_use_exceptions;
- unsigned int isa_use_ext_l32r;
- unsigned int isa_max_insn_size; /* Maximum instruction length. */
- unsigned int debug_num_ibreaks; /* Number of IBREAKs. */
- unsigned int debug_num_dbreaks;
+ unsigned int isa_use_windowed_registers = XSHAL_ABI != XTHAL_ABI_CALL0;
+ unsigned int isa_use_density_instructions = XCHAL_HAVE_DENSITY;
+ unsigned int isa_use_exceptions = XCHAL_HAVE_EXCEPTIONS;
+ unsigned int isa_use_ext_l32r = XSHAL_USE_ABSOLUTE_LITERALS;
+ unsigned int isa_max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE; /* Maximum instruction length. */
+ unsigned int debug_num_ibreaks = XCHAL_NUM_IBREAK; /* Number of IBREAKs. */
+ unsigned int debug_num_dbreaks = XCHAL_NUM_DBREAK;
/* Register map. */
- xtensa_register_t* regmap;
-
- unsigned int num_regs; /* Number of registers in regmap. */
- unsigned int num_pseudo_regs; /* Number of pseudo registers. */
- unsigned int num_aregs; /* Size of register file. */
- unsigned int num_contexts;
-
- int ar_base; /* Register number for AR0. */
- int a0_base; /* Register number for A0 (pseudo). */
- int wb_regnum; /* Register number for WB. */
- int ws_regnum; /* Register number for WS. */
- int pc_regnum; /* Register number for PC. */
- int ps_regnum; /* Register number for PS. */
- int lbeg_regnum; /* Register numbers for count regs. */
- int lend_regnum;
- int lcount_regnum;
- int sar_regnum; /* Register number of SAR. */
- int litbase_regnum; /* Register number of LITBASE. */
-
- int interrupt_regnum; /* Register number for interrupt. */
- int interrupt2_regnum; /* Register number for interrupt2. */
- int cpenable_regnum; /* Register number for cpenable. */
- int debugcause_regnum; /* Register number for debugcause. */
- int exccause_regnum; /* Register number for exccause. */
- int excvaddr_regnum; /* Register number for excvaddr. */
-
- int max_register_raw_size;
- int max_register_virtual_size;
- unsigned long *fp_layout; /* Layout of custom/TIE regs in 'FP' area. */
- unsigned int fp_layout_bytes; /* Size of layout information (in bytes). */
- unsigned long *gregmap;
+ xtensa_register_t *regmap;
+
+ unsigned int num_regs = 0; /* Number of registers in register map. */
+ unsigned int num_nopriv_regs = 0; /* Number of non-privileged registers. */
+ unsigned int num_pseudo_regs = 0; /* Number of pseudo registers. */
+ unsigned int num_aregs = XCHAL_NUM_AREGS; /* Size of register file. */
+ unsigned int num_contexts = XCHAL_NUM_CONTEXTS;
+
+ int ar_base = -1; /* Register number for AR0. */
+ int a0_base = -1; /* Register number for A0 (pseudo). */
+ int wb_regnum = -1; /* Register number for WB. */
+ int ws_regnum = -1; /* Register number for WS. */
+ int pc_regnum = -1; /* Register number for PC. */
+ int ps_regnum = -1; /* Register number for PS. */
+ int lbeg_regnum = -1; /* Register numbers for count regs. */
+ int lend_regnum = -1;
+ int lcount_regnum = -1;
+ int sar_regnum = -1; /* Register number of SAR. */
+ int litbase_regnum = -1; /* Register number of LITBASE. */
+ int threadptr_regnum = -1; /* Register number of THREADPTR. */
+
+ int interrupt_regnum = -1; /* Register number for interrupt. */
+ int interrupt2_regnum = -1; /* Register number for interrupt2. */
+ int cpenable_regnum = -1; /* Register number for cpenable. */
+ int debugcause_regnum = -1; /* Register number for debugcause. */
+ int exccause_regnum = -1; /* Register number for exccause. */
+ int excvaddr_regnum = -1; /* Register number for excvaddr. */
+
+ int max_register_raw_size = 0;
+ int max_register_virtual_size = 0;
+ unsigned long *fp_layout = nullptr; /* Layout of custom/TIE regs in 'FP' area. */
+ unsigned int fp_layout_bytes = 0; /* Size of layout information (in bytes). */
+ unsigned long *gregmap = nullptr;
+
+ /* Cached register types. */
+ struct ctype_cache *type_entries = nullptr;
};
-
-/* Define macros to access some of the gdbarch entries. */
-#define XTENSA_TARGET_FLAGS \
- (gdbarch_tdep (current_gdbarch)->target_flags)
-#define SPILL_LOCATION \
- (gdbarch_tdep (current_gdbarch)->spill_location)
-#define SPILL_SIZE \
- (gdbarch_tdep (current_gdbarch)->spill_size)
-#define CALL_ABI \
- (gdbarch_tdep (current_gdbarch)->call_abi)
-#define ISA_USE_WINDOWED_REGISTERS \
- (gdbarch_tdep (current_gdbarch)->isa_use_windowed_registers)
-#define ISA_USE_DENSITY_INSTRUCTIONS \
- (gdbarch_tdep (current_gdbarch)->isa_use_density_instructions)
-#define ISA_USE_EXCEPTIONS \
- (gdbarch_tdep (current_gdbarch)->isa_use_exceptions)
-#define ISA_USE_EXT_L32R \
- (gdbarch_tdep (current_gdbarch)->isa_use_ext_l32r)
-#define DEBUG_DATA_VADDR_TRAP_COUNT \
- (gdbarch_tdep (current_gdbarch)->debug_data_vaddr_trap_count)
-#define DEBUG_INST_VADDR_TRAP_COUNT \
- (gdbarch_tdep (current_gdbarch)->debug_inst_vaddr_trap_count)
-#define ISA_MAX_INSN_SIZE \
- (gdbarch_tdep (current_gdbarch)->isa_max_insn_size)
-#define DEBUG_NUM_IBREAKS \
- (gdbarch_tdep (current_gdbarch)->debug_num_ibreaks)
-#define DEBUG_NUM_DBREAKS \
- (gdbarch_tdep (current_gdbarch)->debug_num_dbreaks)
-
-#define NUM_AREGS (gdbarch_tdep (current_gdbarch)->num_aregs)
-#define WB_REGNUM (gdbarch_tdep (current_gdbarch)->wb_regnum)
-#define WS_REGNUM (gdbarch_tdep (current_gdbarch)->ws_regnum)
-#define LBEG_REGNUM (gdbarch_tdep (current_gdbarch)->lbeg_regnum)
-#define LEND_REGNUM (gdbarch_tdep (current_gdbarch)->lend_regnum)
-#define LCOUNT_REGNUM (gdbarch_tdep (current_gdbarch)->lcount_regnum)
-#define SAR_REGNUM (gdbarch_tdep (current_gdbarch)->sar_regnum)
-#define REGMAP (gdbarch_tdep (current_gdbarch)->regmap)
-
-#define LITBASE_REGNUM (gdbarch_tdep (current_gdbarch)->litbase_regnum)
-#define DEBUGCAUSE_REGNUM (gdbarch_tdep (current_gdbarch)->debugcause_regnum)
-#define EXCCAUSE_REGNUM (gdbarch_tdep (current_gdbarch)->exccause_regnum)
-#define EXCVADDR_REGNUM (gdbarch_tdep (current_gdbarch)->excvaddr_regnum)
-#define NUM_IBREAKS (gdbarch_tdep (current_gdbarch)->num_ibreaks)
-#define REGMAP_BYTES (gdbarch_tdep (current_gdbarch)->regmap_bytes)
-#define A0_BASE (gdbarch_tdep (current_gdbarch)->a0_base)
-#define AR_BASE (gdbarch_tdep (current_gdbarch)->ar_base)
-#define FP_ALIAS (NUM_REGS + NUM_PSEUDO_REGS)
-#define CALL_ABI (gdbarch_tdep (current_gdbarch)->call_abi)
-#define NUM_CONTEXTS (gdbarch_tdep (current_gdbarch)->num_contexts)
-
-#define FP_LAYOUT (gdbarch_tdep (current_gdbarch)->fp_layout)
-#define FP_LAYOUT_BYTES (gdbarch_tdep (current_gdbarch)->fp_layout_bytes)
-#define GREGMAP (gdbarch_tdep (current_gdbarch)->gregmap)
-
-#define AREGS_MASK (NUM_AREGS - 1)
-#define WB_MASK (AREGS_MASK >> 2)
#define WB_SHIFT 2
/* We assign fixed numbers to the registers of the "current" window
@@ -279,20 +249,4 @@ struct gdbarch_tdep
data structure to their corresponding register in the AR register
file (see xtensa-tdep.c). */
-#define A0_REGNUM (A0_BASE + 0)
-#define A1_REGNUM (A0_BASE + 1)
-#define A2_REGNUM (A0_BASE + 2)
-#define A3_REGNUM (A0_BASE + 3)
-#define A4_REGNUM (A0_BASE + 4)
-#define A5_REGNUM (A0_BASE + 5)
-#define A6_REGNUM (A0_BASE + 6)
-#define A7_REGNUM (A0_BASE + 7)
-#define A8_REGNUM (A0_BASE + 8)
-#define A9_REGNUM (A0_BASE + 9)
-#define A10_REGNUM (A0_BASE + 10)
-#define A11_REGNUM (A0_BASE + 11)
-#define A12_REGNUM (A0_BASE + 12)
-#define A13_REGNUM (A0_BASE + 13)
-#define A14_REGNUM (A0_BASE + 14)
-#define A15_REGNUM (A0_BASE + 15)
-
+#endif /* XTENSA_TDEP_H */