X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=gdbserver%2Flinux-riscv-low.cc;h=6b2902e422d994c7e1d2f40f5b0d1d1276fbba8b;hb=0d02e70b197c786f26175b9a73f94e01d14abdab;hp=092f497b85ab95066650071f59118892833d4f80;hpb=aa8d21c9bb43baaa35f456a3d371942a26cdce4e;p=binutils-gdb.git

diff --git a/gdbserver/linux-riscv-low.cc b/gdbserver/linux-riscv-low.cc
index 092f497b85a..6b2902e422d 100644
--- a/gdbserver/linux-riscv-low.cc
+++ b/gdbserver/linux-riscv-low.cc
@@ -1,6 +1,6 @@
 /* GNU/Linux/RISC-V specific low level interface, for the remote server
    for GDB.
-   Copyright (C) 2020 Free Software Foundation, Inc.
+   Copyright (C) 2020-2022 Free Software Foundation, Inc.
 
    This file is part of GDB.
 
@@ -38,15 +38,47 @@ public:
 
   const regs_info *get_regs_info () override;
 
+  int breakpoint_kind_from_pc (CORE_ADDR *pcptr) override;
+
+  const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override;
+
 protected:
 
   void low_arch_setup () override;
+
+  bool low_cannot_fetch_register (int regno) override;
+
+  bool low_cannot_store_register (int regno) override;
+
+  bool low_fetch_register (regcache *regcache, int regno) override;
+
+  bool low_supports_breakpoints () override;
+
+  CORE_ADDR low_get_pc (regcache *regcache) override;
+
+  void low_set_pc (regcache *regcache, CORE_ADDR newpc) override;
+
+  bool low_breakpoint_at (CORE_ADDR pc) override;
 };
 
 /* The singleton target ops object.  */
 
 static riscv_target the_riscv_target;
 
+bool
+riscv_target::low_cannot_fetch_register (int regno)
+{
+  gdb_assert_not_reached ("linux target op low_cannot_fetch_register "
+			  "is not implemented by the target");
+}
+
+bool
+riscv_target::low_cannot_store_register (int regno)
+{
+  gdb_assert_not_reached ("linux target op low_cannot_store_register "
+			  "is not implemented by the target");
+}
+
 /* Implementation of linux target ops method "low_arch_setup".  */
 
 void
@@ -56,11 +88,11 @@ riscv_target::low_arch_setup ()
 
   const riscv_gdbarch_features features
     = riscv_linux_read_features (lwpid_of (current_thread));
-  target_desc *tdesc = riscv_create_target_description (features);
+  target_desc_up tdesc = riscv_create_target_description (features);
 
   if (!tdesc->expedite_regs)
-    init_target_desc (tdesc, expedite_regs);
-  current_process ()->tdesc = tdesc;
+    init_target_desc (tdesc.get (), expedite_regs);
+  current_process ()->tdesc = tdesc.release ();
 }
 
 /* Collect GPRs from REGCACHE into BUF.  */
@@ -170,23 +202,29 @@ riscv_target::get_regs_info ()
   return &riscv_regs;
 }
 
-/* Implementation of linux_target_ops method "fetch_register".  */
+/* Implementation of linux target ops method "low_fetch_register".  */
 
-static int
-riscv_fetch_register (struct regcache *regcache, int regno)
+bool
+riscv_target::low_fetch_register (regcache *regcache, int regno)
 {
   const struct target_desc *tdesc = regcache->tdesc;
 
   if (regno != find_regno (tdesc, "zero"))
-    return 0;
+    return false;
   supply_register_zeroed (regcache, regno);
-  return 1;
+  return true;
+}
+
+bool
+riscv_target::low_supports_breakpoints ()
+{
+  return true;
 }
 
-/* Implementation of linux_target_ops method "get_pc".  */
+/* Implementation of linux target ops method "low_get_pc".  */
 
-static CORE_ADDR
-riscv_get_pc (struct regcache *regcache)
+CORE_ADDR
+riscv_target::low_get_pc (regcache *regcache)
 {
   elf_gregset_t regset;
 
@@ -196,10 +234,10 @@ riscv_get_pc (struct regcache *regcache)
     return linux_get_pc_32bit (regcache);
 }
 
-/* Implementation of linux_target_ops method "set_pc".  */
+/* Implementation of linux target ops method "low_set_pc".  */
 
-static void
-riscv_set_pc (struct regcache *regcache, CORE_ADDR newpc)
+void
+riscv_target::low_set_pc (regcache *regcache, CORE_ADDR newpc)
 {
   elf_gregset_t regset;
 
@@ -213,10 +251,10 @@ riscv_set_pc (struct regcache *regcache, CORE_ADDR newpc)
 static const uint16_t riscv_ibreakpoint[] = { 0x0073, 0x0010 };
 static const uint16_t riscv_cbreakpoint = 0x9002;
 
-/* Implementation of linux_target_ops method "breakpoint_kind_from_pc".  */
+/* Implementation of target ops method "breakpoint_kind_from_pc".  */
 
-static int
-riscv_breakpoint_kind_from_pc (CORE_ADDR *pcptr)
+int
+riscv_target::breakpoint_kind_from_pc (CORE_ADDR *pcptr)
 {
   union
     {
@@ -232,10 +270,10 @@ riscv_breakpoint_kind_from_pc (CORE_ADDR *pcptr)
     return sizeof (riscv_cbreakpoint);
 }
 
-/* Implementation of linux_target_ops method "sw_breakpoint_from_kind".  */
+/* Implementation of target ops method "sw_breakpoint_from_kind".  */
 
-static const gdb_byte *
-riscv_sw_breakpoint_from_kind (int kind, int *size)
+const gdb_byte *
+riscv_target::sw_breakpoint_from_kind (int kind, int *size)
 {
   *size = kind;
   switch (kind)
@@ -247,10 +285,10 @@ riscv_sw_breakpoint_from_kind (int kind, int *size)
     }
 }
 
-/* Implementation of linux_target_ops method "breakpoint_at".  */
+/* Implementation of linux target ops method "low_breakpoint_at".  */
 
-static int
-riscv_breakpoint_at (CORE_ADDR pc)
+bool
+riscv_target::low_breakpoint_at (CORE_ADDR pc)
 {
   union
     {
@@ -265,26 +303,11 @@ riscv_breakpoint_at (CORE_ADDR pc)
 	      && target_read_memory (pc + sizeof (buf.insn), buf.bytes,
 				     sizeof (buf.insn)) == 0
 	      && buf.insn == riscv_ibreakpoint[1])))
-    return 1;
+    return true;
   else
-    return 0;
+    return false;
 }
 
-/* RISC-V/Linux target operations.  */
-struct linux_target_ops the_low_target =
-{
-  NULL, /* cannot_fetch_register */
-  NULL, /* cannot_store_register */
-  riscv_fetch_register,
-  riscv_get_pc,
-  riscv_set_pc,
-  riscv_breakpoint_kind_from_pc,
-  riscv_sw_breakpoint_from_kind,
-  NULL, /* get_next_pcs */
-  0,    /* decr_pc_after_break */
-  riscv_breakpoint_at,
-};
-
 /* The linux target ops object.  */
 
 linux_process_target *the_linux_target = &the_riscv_target;