X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=include%2Fopcode%2Faarch64.h;h=1e38749c3019b0d7f8803044a2a91c8b1029c54d;hb=93d8990cba700abdf9d2be06a5022e588d097fc8;hp=b45f8c042cdcf8787642bdc607866fa49379b471;hpb=68a642838267d9971f77f9eb487d32044a499c82;p=binutils-gdb.git diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index b45f8c042cd..1e38749c301 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1,6 +1,6 @@ /* AArch64 assembler/disassembler support. - Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. + Copyright (C) 2009-2016 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GNU Binutils. @@ -27,6 +27,10 @@ #include #include +#ifdef __cplusplus +extern "C" { +#endif + /* The offset for pc-relative addressing is currently defined to be 0. */ #define AARCH64_PCREL_OFFSET 0 @@ -34,24 +38,61 @@ typedef uint32_t aarch64_insn; /* The following bitmasks control CPU features. */ #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ +#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */ #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */ #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */ #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */ #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */ +#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */ +#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */ +#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */ +#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */ +#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */ +#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */ +#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */ +#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */ /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ AARCH64_FEATURE_FP \ | AARCH64_FEATURE_SIMD) +#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ + AARCH64_FEATURE_FP \ + | AARCH64_FEATURE_SIMD \ + | AARCH64_FEATURE_CRC \ + | AARCH64_FEATURE_V8_1 \ + | AARCH64_FEATURE_LSE \ + | AARCH64_FEATURE_PAN \ + | AARCH64_FEATURE_LOR \ + | AARCH64_FEATURE_RDMA) +#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ + AARCH64_FEATURE_V8_2 \ + | AARCH64_FEATURE_F16 \ + | AARCH64_FEATURE_RAS \ + | AARCH64_FEATURE_FP \ + | AARCH64_FEATURE_SIMD \ + | AARCH64_FEATURE_CRC \ + | AARCH64_FEATURE_V8_1 \ + | AARCH64_FEATURE_LSE \ + | AARCH64_FEATURE_PAN \ + | AARCH64_FEATURE_LOR \ + | AARCH64_FEATURE_RDMA) + #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */ /* CPU-specific features. */ typedef unsigned long aarch64_feature_set; -#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ +#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \ + ((~(CPU) & (FEAT)) == 0) + +#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \ (((CPU) & (FEAT)) != 0) +#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ + AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT) + #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ do \ { \ @@ -68,9 +109,6 @@ typedef unsigned long aarch64_feature_set; #define AARCH64_FEATURE(core,coproc) ((core) | (coproc)) -#define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \ - (((OPC) & (FEAT)) != 0) - enum aarch64_operand_class { AARCH64_OPND_CLASS_NIL, @@ -106,6 +144,7 @@ enum aarch64_opnd AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ + AARCH64_OPND_PAIRREG, /* Paired register operand. */ AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ @@ -201,6 +240,7 @@ enum aarch64_opnd AARCH64_OPND_BARRIER, /* Barrier operand. */ AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ AARCH64_OPND_PRFOP, /* Prefetch operation. */ + AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ }; /* Qualifier constrains an operand. It either specifies a variant of an @@ -245,6 +285,7 @@ enum aarch64_opnd_qualifier constraint qualifiers for immediate operands wherever possible. */ AARCH64_OPND_QLF_V_8B, AARCH64_OPND_QLF_V_16B, + AARCH64_OPND_QLF_V_2H, AARCH64_OPND_QLF_V_4H, AARCH64_OPND_QLF_V_8H, AARCH64_OPND_QLF_V_2S, @@ -340,6 +381,7 @@ enum aarch64_insn_class loadlit, log_imm, log_shift, + lse_atomic, movewide, pcreladdr, ic_system, @@ -407,6 +449,7 @@ enum aarch64_op OP_SBFX, OP_SBFIZ, OP_BFI, + OP_BFC, /* ARMv8.2. */ OP_UBFIZ, OP_UXTB, OP_UXTH, @@ -495,6 +538,9 @@ struct aarch64_opcode /* Flags providing information about this instruction */ uint32_t flags; + + /* If non-NULL, a function to verify that a given instruction is valid. */ + bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn); }; typedef struct aarch64_opcode aarch64_opcode; @@ -550,7 +596,9 @@ extern aarch64_opcode aarch64_opcode_table[]; #define F_N (1 << 23) /* Opcode dependent field. */ #define F_OD(X) (((X) & 0x7) << 24) -/* Next bit is 27. */ +/* Instruction has the field of 'sz'. */ +#define F_LSE_SZ (1 << 27) +/* Next bit is 28. */ static inline bfd_boolean alias_opcode_p (const aarch64_opcode *opcode) @@ -599,7 +647,7 @@ get_opcode_dependent_value (const aarch64_opcode *opcode) static inline bfd_boolean opcode_has_special_coder (const aarch64_opcode *opcode) { - return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T + return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE : FALSE; } @@ -611,18 +659,37 @@ struct aarch64_name_value_pair }; extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; -extern const struct aarch64_name_value_pair aarch64_sys_regs []; -extern const struct aarch64_name_value_pair aarch64_pstatefields []; extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; extern const struct aarch64_name_value_pair aarch64_prfops [32]; +extern const struct aarch64_name_value_pair aarch64_hint_options []; + +typedef struct +{ + const char * name; + aarch64_insn value; + uint32_t flags; +} aarch64_sys_reg; + +extern const aarch64_sys_reg aarch64_sys_regs []; +extern const aarch64_sys_reg aarch64_pstatefields []; +extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *); +extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set, + const aarch64_sys_reg *); +extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set, + const aarch64_sys_reg *); typedef struct { - const char *template; + const char *name; uint32_t value; - int has_xt; + uint32_t flags ; } aarch64_sys_ins_reg; +extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *); +extern bfd_boolean +aarch64_sys_ins_reg_supported_p (const aarch64_feature_set, + const aarch64_sys_ins_reg *); + extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; @@ -684,8 +751,8 @@ struct aarch64_opnd_info } reg; struct { - unsigned regno : 5; - unsigned index : 4; + unsigned int regno; + int64_t index; } reglane; /* e.g. LVn. */ struct @@ -695,7 +762,7 @@ struct aarch64_opnd_info /* 1 if it is a list of reg element. */ unsigned has_index : 1; /* Lane index; valid only when has_index is 1. */ - unsigned index : 4; + int64_t index; } reglist; /* e.g. immediate or pc relative address offset. */ struct @@ -728,6 +795,7 @@ struct aarch64_opnd_info aarch64_insn pstatefield; const aarch64_sys_ins_reg *sysins_op; const struct aarch64_name_value_pair *barrier; + const struct aarch64_name_value_pair *hint_option; const struct aarch64_name_value_pair *prfop; }; @@ -892,8 +960,11 @@ aarch64_num_of_operands (const aarch64_opcode *); extern int aarch64_stack_pointer_p (const aarch64_opnd_info *); -extern -int aarch64_zero_register_p (const aarch64_opnd_info *); +extern int +aarch64_zero_register_p (const aarch64_opnd_info *); + +extern int +aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean); /* Given an operand qualifier, return the expected data element size of a qualified operand. */ @@ -931,4 +1002,8 @@ aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); #define DEBUG_TRACE_IF(C, M, ...) ; #endif /* DEBUG_AARCH64 */ +#ifdef __cplusplus +} +#endif + #endif /* OPCODE_AARCH64_H */