X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=index.mdwn;h=093dfa824b5ec49a3c6008521d15b6482e088a57;hb=e39d37cb959196fe40e41248d61603c759a5b1e7;hp=cd73b91c86835ce8a3e5ab79239bac35e74f5a28;hpb=5f913723f539c5b9dcec5e9cd2e4464f60bfc1bb;p=libreriscv.git diff --git a/index.mdwn b/index.mdwn index cd73b91c8..093dfa824 100644 --- a/index.mdwn +++ b/index.mdwn @@ -1,66 +1,66 @@ -# Welcome to Libre-SoC ([provisionally renamed](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-January/003580.html) from Libre-RISCV)! +# Welcome to Libre-SOC +(formerly Libre-RISCV) -LibreSOC strives to deliver a fully capable and competitive Libre integrated System on Chip. We want to maximize the degree of trust a customer can place in his or her processor. We do this by providing the customer the freedom to study, modify, and redistribute the SOC source from HDL to VLSI. +> We're building a chip. A fast chip. A safe chip. A trusted chip. -Right now, we're targeting a (quad core, 800mhz, dual issue, GPU, VPU, [and later an ML inference core] ) SOC. +> A chip with lots of peripherals. And a VPU. And a 3D GPU... -## Why a Libre SOC? +> Oh and here, have the source code... -Its quite hard to guarantee that a performant processors(think pipelined, out-of-order) are functionally perfectly correct. In fact, it often turns out that they [aren’t](https://meltdownattack.com). +Sounds cool? Learn more about the [why](why_a_libresoc) behind Libre-SOC +and [our mission](The_Mission). -There are entire [dissertations](http://www.kroening.com/diss/diss-kroe.pdf) dedicated to the subject matter of merely functionally verifying a pipeline(this doesn’t even consider out of order execution). +# Our Team -Given the fact that performant bug-free processors no longer exist, how can you trust your processor? The next best thing is to have access to a processor’s design files. Not only have access to them, you must have the freedom to study and improve them. +We are proud of our talented and diverse [team](about_us). -Such a processor is referred to as a Libre processor. However, processors themselves are only a part of the picture. Nowadays, most contemporary computing tasks involve artificial intelligence, media consumption, wireless connectivity, etc. Hence, the need to deliver and entire LibreSOC. +# How Can I Help? -## Benefits: Privacy, Safety-Critical, Peace of Mind... -Our LibreSOC will not have backdoors that plague modern [processors](https://www.csoonline.com/article/3220476/researchers-say-now-you-too-can-disable-intel-me-backdoor-thanks-to-the-nsa.html). +If you would like to fund us, see [[funding]]. We currently have some +funding and always appreciate more! If you are a Corporation or an +individual you can donate tax-free to NLNet, and they can in turn gift +our developers. Contact lkcl@lkcl.net for more information. -There is a very real need for reliable safety critical processors(think airplane, smart car, pacemaker...). -LibreSOC poses to you that it is impossible to trust a processor in a safety critical environment without both access -to that processor's source and a cycle accurate HDL simulator that guarantees developers their code behaves as they -expect. An ISA level simulator is no longer satisfactory. +If you want to write code with us, keep reading. If you want to *learn* so that you can write code with us, see below. -Refer to this [IEEE article](https://ieeexplore.ieee.org/document/4519604) by Cyberphysical System expert Ed-Lee for more details. - -## Still Have Questions? -Read about the business and practical benefits of a LibreSOC below. - -[[why_a_libresoc]] - - -# Join us in Realizing the First Market Ready LibreSOC! - -First. join the +1. First, join the [mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev), introduce yourself, and read through [recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/) and the [[charter]]. - -The next thing you should do is read through the [bugs +2. The next thing you should do is read through the [bugs list](http://bugs.libre-riscv.org) and see if there are any bugs that pique your interest. - -We do have funding available (see [[nlnet]]) upon completion of issues - +3. After that, go ahead and take a look at the resources section below. +Try and clone a repository with +``git clone https://git.libre-riscv.org/git/repositoryname.git`` +4. If you plan to do HDL work, you should familiarize yourself with our + [[HDL_workflow]]. +5. We do have funding available (see [[nlnet]]) upon completion of issues - we are also working on procuring more funding which gets the project to nanometre scale tapeout. - -After all this, if you feel that Libre-SoC is a good cause that -you would like to contribute to, add yourself to the [[current_members]] +6. After all this, if you feel that Libre-SOC is a something that +you would like to contribute to, add yourself to the [current_members](about_us) page, fill in some information about yourself, and join the mailing list and say hello. Also note that you can edit this wiki. See the last section of this page. +## How can I learn? + +The whole purpose of this project is to be a learning environment as well as an actual business. If you want to learn how to do ASIC design, with a view to contributing or starting your own ASIC business, start here: [[3d_gpu/tutorial]]. Yes, really: do not let anyone tell you that you can't learn this stuff too. + +Along the way, if you find any resources or links that you found particularly helpful, please add them to that page so that other people can also benefit. + ## Needed Skills Most labor is currently being applied to developing the GPU portion of -the Libre-SoC. +the Libre-SOC. The highest priority needed at the moment is a c++ engineer to work on a MESA 3D driver. This will begin life similar to SwiftShader however -retaining the vectorisation and predication intrinsics as well as hardware accelerated opcodes (all of which SwiftShader lacks) +retaining the vectorisation and predication intrinsics as well as hardware +accelerated opcodes (all of which SwiftShader lacks) Medium to long-term we need HDL engineers. Particularly those familiar with nMigen or just python. Most of the techniques being used require @@ -72,49 +72,10 @@ design. See [[HDL_workflow]] Also, individuals with experience in formal mathematical verification are quite welcome. -TODO: add a list of upcoming project tasks/milestones (link to -bugtracker). - -# Resources - -* Mailing Lists - - Archives at -* Git repositories - may be cloned publicly with - git clone https://git.libre-riscv.org/git/repositoryname.git -* Bugzilla at -* Kazan (Vulkan driver) at -* Further Information [[resources]] - -# Main Pages - -* Libre-SoC [[charter]] -* [[shakti/m_class]] -* [[alt_rvp]] -* [[3d_gpu]] -* [[vpu]] -* [[simple_v_extension]] -* [[zfpacc_proposal]] -* [[ztrans_proposal]] -* [[simple_v_extension/specification/mv.x]] -* [[simple_v_extension/specification/ld.x]] -* Specifications and [[resources]] - -# Spike Emulator -* [Set-Up Instructions][1] - -[1]: https://libre-riscv.org/3d_gpu/spike_sv/ - -# Current Members - -[[current_members]] - -# Wiki Structure - -This is a publicly editable wiki. - -All wikis are supposed to have a [[SandBox]], so this one does too. +List of upcoming project tasks/milestones: -This wiki is powered by [[ikiwiki]]. +* [Upcoming tasks][1] +* [NLNet Milestones][2] -This is the sitemap: [[sitemap]] +[1]: http://bugs.libre-riscv.org/describecomponents.cgi?product=Libre%20Shakti%20M-Class +[2]: http://bugs.libre-riscv.org/describecomponents.cgi?product=Libre%20Shakti%20M-Class