X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=index.mdwn;h=5ac9debd0e5c17dfa11d9e1dee7c8a3bf34d700d;hb=a3e0ed56b3b6b9e170841da4bdf5ef58cf961757;hp=88548043df1c8f12175a5fec684ce786602beb6b;hpb=fc1b5e5d767bc507063c70d4e724cc459573b2a3;p=libreriscv.git diff --git a/index.mdwn b/index.mdwn index 88548043d..5ac9debd0 100644 --- a/index.mdwn +++ b/index.mdwn @@ -1,51 +1,86 @@ -# Welcome to Libre-SoC! +# Welcome to LibreSoC -Libre-RISCV is an effort to develop an completely open/Libre SOC that is open to the bedrock! +> We're building a chip. A fast chip. A safe chip. A trusted chip. -This is a publicly editable wiki. +> A chip with lots of peripherals. And a VPU. And a 3D GPU... -All wikis are supposed to have a [[SandBox]], so this one does too. +> Oh and here, have the source code... -This wiki is powered by [[ikiwiki]]. +Sounds cool? Learn more about the [why](why_a_libresoc) behind LibreSOC and [our mission](The_Mission). -This is the sitemap: [[sitemap]] +# Our Team + +We are proud of our talented and diverse [team](about_us). + +# How Can I Help? + +If you would like to fund us, see [[funding]]. We currently have some funding and always appreciate more! If you are a Corporation or an individual you can donate tax-free to NLNet, and they can in turn gift our developers. Contact lkcl@lkcl.net for more information. + +If you want to write code with us, keep reading. + +1. First, join the +[mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev), +introduce yourself, and read through +[recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/) +and the [[charter]]. + +2. The next thing you should do is read through the [bugs +list](http://bugs.libre-riscv.org) and see if there are any bugs that +pique your interest. ----- +3. After that, go ahead and take a look at the resources section below. +Try and clone a repository with ``git clone https://git.libre-riscv.org/git/repositoryname.git`` -# Joining/Onboarding Process +4. If you plan to do HDL work, you should familiarize yourself with our [[HDL_workflow]]. -This process probably needs some improvement, but the basic -idea is to join the [mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev), introduce yourself, -and read through [recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/). +5. We do have funding available (see [[nlnet]]) upon completion of issues - +we are also working on procuring more funding which gets the project to +nanometre scale tapeout. -The next thing you should do is read through the [bugs list](http://bugs.libre-riscv.org) and see if there are any bugs that pique your interest. +6. After all this, if you feel that Libre-SoC is a good cause that +you would like to contribute to, add yourself to the [current_members](about_us) +page, fill in some information about yourself, and join the mailing list +and say hello. -We do have funding available (see [[nlnet]]) upon completion of issues - we are also working on procuring more funding which gets the project to nanometre scale tapeout. +Also note that you can edit this wiki. See the last section of this page. ## Needed Skills -Most labor is currently being applied to developing the GPU portion of the LibreSOC. +Most labor is currently being applied to developing the GPU portion of +the Libre-SoC. -We mainly need HDL engineers at the moment. Particularly those familiar with nMigen. +The highest priority needed at the moment is a c++ engineer to work on +a MESA 3D driver. This will begin life similar to SwiftShader however +retaining the vectorisation and predication intrinsics as well as hardware accelerated opcodes (all of which SwiftShader lacks) -Also, individuals with experience in formal verification are quite welcome. +Medium to long-term we need HDL engineers. Particularly those familiar +with nMigen or just python. Most of the techniques being used require +software engineering skills (OO design, polymorphism) than they do more +traditional HDL programming skills. Basically if you have experience in 2 +of the following you'll do fine: python, nmigen, verilog/VHDL/gate-level +design. See [[HDL_workflow]] -TODO: add a list of upcoming project tasks/milestones +Also, individuals with experience in formal mathematical verification +are quite welcome. + +TODO: add a list of upcoming project tasks/milestones (link to +bugtracker). # Resources -* Mailing Lists - - Archives at -* Git repositories - may be cloned publicly with - git clone https://git.libre-riscv.org/git/repositoryname.git -* Bugzilla at -* Kazan (Vulkan driver) at -* Further Information [[resources]] +| Resource | Link | +| --- | --- | +| Bugs and Tasks | | +| Mailing Lists | | +| Archives | | +| Git repositories | | +| Kazan (Vulkan driver) | | +| Standards | [[standards]] | +| Further Information | [[resources]] | # Main Pages -* Libre-RISCV [[charter]] +* Libre-SoC [[charter]] * [[shakti/m_class]] * [[alt_rvp]] * [[3d_gpu]] @@ -55,9 +90,20 @@ TODO: add a list of upcoming project tasks/milestones * [[ztrans_proposal]] * [[simple_v_extension/specification/mv.x]] * [[simple_v_extension/specification/ld.x]] +* [[future_feature_proposals]] * Specifications and [[resources]] # Spike Emulator * [Set-Up Instructions][1] [1]: https://libre-riscv.org/3d_gpu/spike_sv/ + +# Wiki Structure + +This is a publicly editable wiki. + +All wikis are supposed to have a [[SandBox]], so this one does too. + +This wiki is powered by [[ikiwiki]]. + +This is the sitemap: [[sitemap]]