X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=index.mdwn;h=d304b08da82d45551013310b4b37cb9c6dc1fdd7;hb=9a3152108ae94e04c416f8f8e616741ee98e5ccd;hp=5dc2dd7feb3cd6f45e6af29361a13e393e2f1d51;hpb=0a9c686fac0716010d97a9c170f23c12de949950;p=libreriscv.git diff --git a/index.mdwn b/index.mdwn index 5dc2dd7fe..d304b08da 100644 --- a/index.mdwn +++ b/index.mdwn @@ -1,54 +1,39 @@ -# Welcome to Libre-SoC ([provisionally renamed](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-January/003580.html) from Libre-RISCV)! +# Welcome to LibreSoC -LibreSOC strives to deliver a fully capable and competitive mass volume Libre integrated System on Chip for use in chromebooks, smartphone, tablets and industrial boards. We want to maximize the degree of trust a customer can place in their processor. We do this by providing the customer the freedom to study, modify, and redistribute the the bootloader and Operating System full source code *and* the full SoC source from HDL to VLSI. +> We're building a chip. A fast chip. A safe chip. A trusted chip. -Right now, we're targeting a (quad core, 800mhz, dual issue, GPU, VPU, [and later an ML inference core] ) SOC. +> A chip with lots of peripherals. And a gpu. And an AI accelerator... -See our [[3d_gpu/mission_statement]] +> Oh and here, have the source code... -## Why a Libre SOC? +Sounds cool? Learn more [here](who_we_are) -Its quite hard to guarantee that a performant processors (think pipelined, out-of-order) are functionally perfectly correct. In fact, it often turns out that they [aren’t](https://meltdownattack.com). +# Our Team -There are entire [dissertations](http://www.kroening.com/diss/diss-kroe.pdf) dedicated to the subject matter of merely functionally verifying a pipeline (this doesn’t even consider out of order execution). +We are proud of our talented and diverse [team](current_members). -Given the fact that performant bug-free processors no longer exist, how can you trust your processor? The next best thing is to have access to a processor’s design files. Not only have access to them, you must have the freedom to study and improve them. +# How Can I Help? -Such a processor is referred to as a Libre processor. However, processors themselves are only a part of the picture. Nowadays, most contemporary computing tasks involve artificial intelligence, media consumption, wireless connectivity, etc... Thus, we must deliver an entire LibreSOC. - -## Benefits: Privacy, Safety-Critical, Peace of Mind... -Our LibreSOC will not have backdoors that plague modern [processors](https://www.csoonline.com/article/3220476/researchers-say-now-you-too-can-disable-intel-me-backdoor-thanks-to-the-nsa.html). - -There is a very real need for reliable safety critical processors (think airplane, smart car, nuclear power plant, pacemaker...). -LibreSOC posits that it is impossible to trust a processor in a safety critical environment without both access -to that processor's source and a cycle accurate HDL simulator that guarantees developers their code behaves as they -expect. An ISA level simulator is no longer satisfactory. - -Refer to this [IEEE article](https://ieeexplore.ieee.org/document/4519604) by Cyberphysical System expert Ed-Lee for more details. - -## Still Have Questions? - -Read about the business and practical benefits of a LibreSOC below. - -[[why_a_libresoc]] - -# Join us in Realizing the First Market Ready LibreSOC! - -First, join the +1. First, join the [mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev), introduce yourself, and read through [recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/) and the [[charter]]. -The next thing you should do is read through the [bugs +2. The next thing you should do is read through the [bugs list](http://bugs.libre-riscv.org) and see if there are any bugs that pique your interest. -We do have funding available (see [[nlnet]]) upon completion of issues - +3. After that, go ahead and take a look at the resources section below. +Try and clone a repository with ``git clone https://git.libre-riscv.org/git/repositoryname.git`` + +4. If you plan to do HDL work, you should familiarize yourself with our [[HDL_workflow]]. + +5. We do have funding available (see [[nlnet]]) upon completion of issues - we are also working on procuring more funding which gets the project to nanometre scale tapeout. -After all this, if you feel that Libre-SoC is a good cause that +6. After all this, if you feel that Libre-SoC is a good cause that you would like to contribute to, add yourself to the [[current_members]] page, fill in some information about yourself, and join the mailing list and say hello. @@ -79,14 +64,14 @@ bugtracker). # Resources -* Mailing Lists - - Archives at -* Git repositories - may be cloned publicly with - git clone https://git.libre-riscv.org/git/repositoryname.git -* Bugzilla at -* Kazan (Vulkan driver) at -* Further Information [[resources]] +| Resource | Link | +| --- | --- | +| Bugs and Tasks | | +| Mailing Lists | | +| Archives | | +| Git repositories | | +| Kazan (Vulkan driver) | | +| Further Information | [[resources]] | # Main Pages @@ -107,10 +92,6 @@ bugtracker). [1]: https://libre-riscv.org/3d_gpu/spike_sv/ -# Current Members - -[[current_members]] - # Wiki Structure This is a publicly editable wiki.