X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Fmacros%2Fscalar%2Ftest_macros.h;h=11645fee5b283b969efb0a5fbb1ebd71259ba426;hb=acc35f32c788fdcbb854f8fb6d74026050ced273;hp=cd7d21d1385c262e4ade9e7dc4cff37b3022d72f;hpb=2129261a6567a0d9705f7b7c7609d22b1d183b00;p=riscv-tests.git

diff --git a/isa/macros/scalar/test_macros.h b/isa/macros/scalar/test_macros.h
index cd7d21d..11645fe 100644
--- a/isa/macros/scalar/test_macros.h
+++ b/isa/macros/scalar/test_macros.h
@@ -89,34 +89,6 @@ test_ ## testnum: \
       inst x0, x1, SEXT_IMM(imm); \
     )
 
-#-----------------------------------------------------------------------
-# Tests for vector config instructions
-#-----------------------------------------------------------------------
-
-#define TEST_VSETCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \
-    TEST_CASE( testnum, x1, result, \
-      li x1, (bank << 12); \
-      vsetcfg x1,nxpr,nfpr; \
-      li x1, vl; \
-      vsetvl x1,x1; \
-    )
-
-#define TEST_VVCFG( testnum, nxpr, nfpr, bank, vl, result ) \
-    TEST_CASE( testnum, x1, result, \
-      li x1, (bank << 12) | (nfpr << 6) | nxpr; \
-      vsetcfg x1; \
-      li x1, vl; \
-      vsetvl x1,x1; \
-    )
-
-#define TEST_VSETVL( testnum, nxpr, nfpr, bank, vl, result ) \
-    TEST_CASE( testnum, x1, result, \
-      li x1, (bank << 12); \
-      vsetcfg x1,nxpr,nfpr; \
-      li x1, vl; \
-      vsetvl x1, x1; \
-    )
-
 #-----------------------------------------------------------------------
 # Tests for an instruction with register operands
 #-----------------------------------------------------------------------