X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Frv32ua%2Famomin_w.S;h=cbd88e64bfc9f4ad2be02dad0de3d124e8201202;hb=d5fa5fa7c233a219d9b2c1b1d0fbcab9bba986c7;hp=a6a094728a7b32ffc106eb55bc7c2eb01456867d;hpb=089f4aae4836af1f3f530fbedc3a43a685eae0d1;p=riscv-tests.git

diff --git a/isa/rv32ua/amomin_w.S b/isa/rv32ua/amomin_w.S
index a6a0947..cbd88e6 100644
--- a/isa/rv32ua/amomin_w.S
+++ b/isa/rv32ua/amomin_w.S
@@ -1,49 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# amomin_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomin.w instruction.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
-  TEST_CASE(2, a4, 0x80000000, \
-    li a0, 0x80000000; \
-    li a1, 0xfffff800; \
-    la a3, amo_operand; \
-    sw a0, 0(a3); \
-    amomin.w	a4, a1, 0(a3); \
-  )
-
-  TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3))
-
-  TEST_CASE(4, a4, 0, \
-    li a1, 0xffffffff; \
-    sw x0, 0(a3); \
-    amomin.w	a4, a1, 0(a3); \
-  )
-
-  TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3))
-
-  TEST_PASSFAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-RVTEST_DATA_END
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
 
-  .bss
-  .align 3
-amo_operand:
-  .dword 0
-  .skip 65536
+#include "../rv64ua/amomin_w.S"