X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Frv64mi%2Fdirty.S;h=0314cf5acbfc64914e89b388e90fc856f088ae0b;hb=d7bd2474c4474f0ca69c6d0adc4dd3501c91c5bc;hp=1cf429a235ef8107c36d10af10e210b3f428a61b;hpb=74fa7fbd09701e8a63b616cd9a8f78c23a43cbb3;p=riscv-tests.git

diff --git a/isa/rv64mi/dirty.S b/isa/rv64mi/dirty.S
index 1cf429a..0314cf5 100644
--- a/isa/rv64mi/dirty.S
+++ b/isa/rv64mi/dirty.S
@@ -15,32 +15,36 @@ RVTEST_CODE_BEGIN
 
   # Turn on VM with superpage identity mapping
   la a1, page_table_1
+  srl a1, a1, RISCV_PGSHIFT
+  la a2, page_table_2
+  srl a2, a2, RISCV_PGSHIFT
   csrw sptbr, a1
   sfence.vm
-  li a1, ((MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV39) | ((MSTATUS_PRV1 & ~(MSTATUS_PRV1<<1)) * PRV_S)
+  li a1, ((MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV39) | ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S)
   csrs mstatus, a1
-  la a1, 1f
+  la a1, 1f - DRAM_BASE
   csrw mepc, a1
-  eret
+  la a1, stvec_handler - DRAM_BASE
+  csrw stvec, a1
+  mret
 1:
 
   # Try a faulting store to make sure dirty bit is not set
   li TESTNUM, 2
   li t0, 1
-  sd t0, dummy, t1
+  sw t0, dummy, t1
 
   # Load new page table
   li TESTNUM, 3
-  la t0, page_table_2
-  csrw sptbr, t0
+  csrw sptbr, a2
   sfence.vm
 
   # Try a non-faulting store to make sure dirty bit is set
-  sd t0, dummy, t1
+  sw t0, dummy, t1
 
   # Make sure R and D bits are set
   lw t0, page_table_2
-  li t1, PTE_R | PTE_D
+  li t1, PTE_A | PTE_D
   and t0, t0, t1
   bne t0, t1, die
   
@@ -48,13 +52,14 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
+  .align 2
 stvec_handler:
   csrr t0, scause
   li t1, 2
   bne TESTNUM, t1, 1f
   # Make sure R bit is set
   lw t0, page_table_1
-  li t1, PTE_R
+  li t1, PTE_A
   and t0, t0, t1
   bne t0, t1, die
 
@@ -72,11 +77,17 @@ stvec_handler:
 die:
   RVTEST_FAIL
 
-.data
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
 .align 12
-page_table_1: .dword PTE_TYPE_US_SRX
+page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X
 dummy: .dword 0
 .align 12
-page_table_2: .dword PTE_TYPE_US_SRWX
+page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_W
 
-RVTEST_CODE_END
+RVTEST_DATA_END