X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Frv64mi%2Fipi.S;h=71783107e250478b817b99b5a815a580f5a108c1;hb=9fc686ae1488a596d0bed561a750396911e71b01;hp=8aca6657753397511034c252c5e94384a034b158;hpb=08486cb632ef704709a89fc6bab5842bec4c2547;p=riscv-tests.git

diff --git a/isa/rv64mi/ipi.S b/isa/rv64mi/ipi.S
index 8aca665..7178310 100644
--- a/isa/rv64mi/ipi.S
+++ b/isa/rv64mi/ipi.S
@@ -14,7 +14,7 @@ RVTEST_RV64M
 RVTEST_CODE_BEGIN
 
   # enable interrupts
-  csrs mstatus, MSTATUS_IE
+  csrs mstatus, MSTATUS_MIE
   csrs mie, MIP_MSIP
 
   # get a unique core id