X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Frv64si%2Fdirty.S;h=0314cf5acbfc64914e89b388e90fc856f088ae0b;hb=8ad0c87b54dc1b52548c62834d2597b573e60848;hp=78e333b62995714cccf891d4c5013a3fcf301840;hpb=211d78276b07b17f831cefaf79961d3e6dad3c90;p=riscv-tests.git

diff --git a/isa/rv64si/dirty.S b/isa/rv64si/dirty.S
index 78e333b..0314cf5 100644
--- a/isa/rv64si/dirty.S
+++ b/isa/rv64si/dirty.S
@@ -14,35 +14,37 @@ RVTEST_RV64M
 RVTEST_CODE_BEGIN
 
   # Turn on VM with superpage identity mapping
-  la a1, handler
-  csrw stvec, a1
   la a1, page_table_1
+  srl a1, a1, RISCV_PGSHIFT
+  la a2, page_table_2
+  srl a2, a2, RISCV_PGSHIFT
   csrw sptbr, a1
   sfence.vm
-  li a1, (MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV43
+  li a1, ((MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV39) | ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S)
   csrs mstatus, a1
-  la a1, 1f
+  la a1, 1f - DRAM_BASE
   csrw mepc, a1
-  eret
+  la a1, stvec_handler - DRAM_BASE
+  csrw stvec, a1
+  mret
 1:
 
   # Try a faulting store to make sure dirty bit is not set
   li TESTNUM, 2
   li t0, 1
-  sd t0, dummy, t1
+  sw t0, dummy, t1
 
   # Load new page table
   li TESTNUM, 3
-  la t0, page_table_2
-  csrw sptbr, t0
+  csrw sptbr, a2
   sfence.vm
 
   # Try a non-faulting store to make sure dirty bit is set
-  sd t0, dummy, t1
+  sw t0, dummy, t1
 
   # Make sure R and D bits are set
   lw t0, page_table_2
-  li t1, PTE_R | PTE_D
+  li t1, PTE_A | PTE_D
   and t0, t0, t1
   bne t0, t1, die
   
@@ -50,13 +52,14 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-handler:
+  .align 2
+stvec_handler:
   csrr t0, scause
   li t1, 2
   bne TESTNUM, t1, 1f
   # Make sure R bit is set
   lw t0, page_table_1
-  li t1, PTE_R
+  li t1, PTE_A
   and t0, t0, t1
   bne t0, t1, die
 
@@ -74,11 +77,17 @@ handler:
 die:
   RVTEST_FAIL
 
-.data
-.align 13
-page_table_1: .dword PTE_V | PTE_SX | PTE_SR
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+.align 12
+page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X
 dummy: .dword 0
-.align 13
-page_table_2: .dword PTE_V | PTE_SX | PTE_SR | PTE_SW
+.align 12
+page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_W
 
-RVTEST_CODE_END
+RVTEST_DATA_END