X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Frv64si%2Fma_fetch.S;h=cd5a22d72077a768ff6e9753ec56c7e84fbc2990;hb=6cd865488a4ef49f0f68f46ef619f097a0ae9ec0;hp=594345687a83fc1436ae7cfc3e02bdfe7780fbb0;hpb=d9b4071ea4a9a2fe84a51443250184f51e931ac2;p=riscv-tests.git

diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S
index 5943456..cd5a22d 100644
--- a/isa/rv64si/ma_fetch.S
+++ b/isa/rv64si/ma_fetch.S
@@ -23,6 +23,7 @@ RVTEST_CODE_BEGIN
   #define stvec_handler mtvec_handler
 #endif
 
+  .align 2
   .option norvc
 
   # Without RVC, the jalr should trap, and the handler will skip ahead.