X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Frv64si%2Fscall.S;h=1f5e6b79fa286f9d486f1274f320fadd2e1516d2;hb=ea53b10a55e523672340af4bf5ae710e3e314a32;hp=703de0b5a8895efbb60dcc5efb599233453e3b1f;hpb=e3f64eb4fa0bf94f4ffa063aaf182f092d1e166e;p=riscv-tests.git

diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S
index 703de0b..1f5e6b7 100644
--- a/isa/rv64si/scall.S
+++ b/isa/rv64si/scall.S
@@ -18,6 +18,7 @@ RVTEST_CODE_BEGIN
   #define sstatus mstatus
   #define scause mcause
   #define sepc mepc
+  #define sret mret
   #define stvec_handler mtvec_handler
   #undef SSTATUS_SPP
   #define SSTATUS_SPP MSTATUS_MPP
@@ -25,20 +26,39 @@ RVTEST_CODE_BEGIN
 
   li TESTNUM, 2
 
+  # This is the expected trap code.
+  li t1, CAUSE_USER_ECALL
+
+#ifdef __MACHINE_MODE
+  # If running in M mode, use mstatus.MPP to check existence of U mode.
+  # Otherwise, if in S mode, then U mode must exist and we don't need to check.
+  li t0, MSTATUS_MPP
+  csrc mstatus, t0
+  csrr t1, mstatus
+  and t0, t0, t1
+  beqz t0, 1f
+
+  # If U mode doesn't exist, mcause should indicate ECALL from M mode.
+  li t1, CAUSE_MACHINE_ECALL
+#endif
+
+1:
   li t0, SSTATUS_SPP
   csrc sstatus, t0
   la t0, 1f
   csrw sepc, t0
-  eret
+  sret
 1:
 
+  li TESTNUM, 1
   scall
   j fail
 
   TEST_PASSFAIL
 
+  .align 2
+  .global stvec_handler
 stvec_handler:
-  li t1, CAUSE_USER_ECALL
   csrr t0, scause
   bne t0, t1, fail
   j pass