X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Frv64sv%2Fillegal_vt_regid.S;h=e74b614d5f345cc3ad96ca6bf89066b14cee8e63;hb=9e4b081d4a219c4eea1a7e979c316a0ff1cd7cdc;hp=24745dc62f99cd1f25bb0dfe0064fa432859b416;hpb=a398a9baeccebbf7b8c7bd04edaac5e0d02cd7bf;p=riscv-tests.git

diff --git a/isa/rv64sv/illegal_vt_regid.S b/isa/rv64sv/illegal_vt_regid.S
index 24745dc..e74b614 100644
--- a/isa/rv64sv/illegal_vt_regid.S
+++ b/isa/rv64sv/illegal_vt_regid.S
@@ -23,6 +23,10 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
+# the handler gets rewritten for every test, but need this for the framework
+stvec_handler:
+  j fail
+
 RVTEST_CODE_END
 
   .data