X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Frv64sv%2Fma_utld.S;h=5ea6ee6d52a92ced7b34d05fde2d4763cdc4b732;hb=9e4b081d4a219c4eea1a7e979c316a0ff1cd7cdc;hp=a71c4a1baad5a82a9880a97094e0a07adcbcc83d;hpb=81ad66f25ce4c15180e558696961bd8eaf967fea;p=riscv-tests.git

diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S
index a71c4a1..5ea6ee6 100644
--- a/isa/rv64sv/ma_utld.S
+++ b/isa/rv64sv/ma_utld.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # ma_utld.S
 #-----------------------------------------------------------------------------
@@ -8,26 +10,18 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  mfpcr a3,cr0
-  li a4,1
-  slli a5,a4,8
-  or a3,a3,a4 # enable traps
-  mtpcr a3,cr0
-
-  la a3,handler
-  mtpcr a3,cr3 # set exception handler
-
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3, dest+1
   vmsv vx1, a3
   lui a0,%hi(vtcode1)
   vf %lo(vtcode1)(a0)
-  fence.v.l
+  fence
 
 vtcode1:
   lw x2, 0(x1)
@@ -37,24 +31,25 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
-  mfpcr a3,cr6
-  li a4,28
+  csrr a3, scause
+  li a4,HWACHA_CAUSE_MISALIGNED_LOAD
   bne a3,a4,fail
 
   # check vec irq aux
-  mfpcr a3,cr2
+  csrr a3, sbadaddr
   la a4,dest+1
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
+  vsetcfg 32,0
   li a3,4
-  vvcfgivl a3,a3,32,0
+  vsetvl a3,a3
 
   la a3,src1
   la a4,src2
@@ -64,20 +59,20 @@ handler:
   vf %lo(vtcode2)(a0)
   la a5,dest
   vsd vx2,a5
-  fence.v.l
+  fence
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL