X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Frv64sv%2Fma_vt_inst.S;h=a2579425e0abf020104a7200d29cc574aca28377;hb=9e4b081d4a219c4eea1a7e979c316a0ff1cd7cdc;hp=6a178257e9bebcaaabdca1c5c0e4a32c495700a9;hpb=160bdaa323bc8f8e651f9f546822336cf17d92f5;p=riscv-tests.git

diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
index 6a17825..a257942 100644
--- a/isa/rv64sv/ma_vt_inst.S
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -10,21 +10,9 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
-  la a3,handler
-  csrw evec,a3
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -37,18 +25,18 @@ vtcode1:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH
   bne a3,a4,fail
 
   # check badvaddr
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4,vtcode1+2
   andi a3, a3, -4 # mask off lower bits so that may
   andi a4, a4, -4 # ignore impl. specific behavior