X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Frv64ui%2Fsv_addi_predicated_subvl.S;fp=isa%2Frv64ui%2Fsv_addi_predicated_subvl.S;h=4cd3ec07448f9d18f0c0f31bf4cc885623117a8a;hb=98794f4103f9cf6f1b21c569e14b65bc1ab810a6;hp=0000000000000000000000000000000000000000;hpb=a924a13af9980c1c6f2c90b66856f9d20bf1daa3;p=riscv-tests.git

diff --git a/isa/rv64ui/sv_addi_predicated_subvl.S b/isa/rv64ui/sv_addi_predicated_subvl.S
new file mode 100644
index 0000000..4cd3ec0
--- /dev/null
+++ b/isa/rv64ui/sv_addi_predicated_subvl.S
@@ -0,0 +1,93 @@
+#include "riscv_test.h"
+#include "sv_test_macros.h"
+
+RVTEST_RV64U        # Define TVM used by program.
+
+#define SV_PREDICATION_TEST( pred, inv, zero, expect1, expect2 ) \
+                                                        \
+        SV_LDD_DATA( x2, testdata   , 0);               \
+        SV_LDD_DATA( x3, testdata+8 , 0);               \
+        SV_LDD_DATA( x4, testdata+16, 0);               \
+        SV_LDD_DATA( x5, testdata+24, 0);               \
+                                                        \
+        li      x6, pred;                               \
+                                                        \
+        SET_SV_MVL( 2);                                  \
+        SET_SV_CSR( 1, 3, SV_W_32BIT, 3, 1);             \
+        SET_SV_PRED_CSR( 1, 3, zero, inv, 6, 0);         \
+        SET_SV_VL( 2);                                   \
+        SET_SV_SUBVL( 2);                                \
+                                                        \
+        addi    x3, x3, 1;                              \
+                                                        \
+        CLR_SV_CSRS();                                  \
+        SET_SV_VL( 1);                                   \
+        SET_SV_MVL( 1);                                  \
+        SET_SV_SUBVL( 1);                                \
+                                                        \
+        TEST_SV_IMM( x2, 1001);                         \
+        TEST_SV_IMM( x3, expect1);                       \
+        TEST_SV_IMM( x4, expect2);                       \
+        TEST_SV_IMM( x5, 1002);
+
+
+# SV test: vector-vector add
+#
+# sets up x3 and x4 with data, sets VL to 2, and carries out
+# an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
+
+# Test code region.
+RVTEST_CODE_BEGIN   # Start of test code.
+
+        # no zeroing, no inversion
+/*
+        SV_PREDICATION_TEST( 0x1, 0, 0, 0x4200000043, 0x4300000044 ) 
+
+        SV_PREDICATION_TEST( 0x2, 0, 0, 41, 43 ) 
+*/
+        //SV_PREDICATION_TEST( 0x3, 0, 0, 0x4200000043, 0x4400000045 ) 
+        SV_PREDICATION_TEST( 0x0, 0, 0, 0x4100000042, 0x4300000044 ) 
+/*
+        # zeroing, no inversion
+        SV_PREDICATION_TEST( 0x1, 0, 1, 42, 0 ) 
+        SV_PREDICATION_TEST( 0x2, 0, 1, 0, 43 ) 
+        SV_PREDICATION_TEST( 0x3, 0, 1, 42, 43 ) 
+        SV_PREDICATION_TEST( 0x0, 0, 1, 0, 0 ) 
+
+        # no zeroing, inversion
+        SV_PREDICATION_TEST( 0x2, 1, 0, 42, 42 ) 
+        SV_PREDICATION_TEST( 0x1, 1, 0, 41, 43 ) 
+        SV_PREDICATION_TEST( 0x0, 1, 0, 42, 43 ) 
+        SV_PREDICATION_TEST( 0x3, 1, 0, 41, 42 ) 
+
+        # zeroing, inversion
+        SV_PREDICATION_TEST( 0x2, 1, 1, 42, 0 ) 
+        SV_PREDICATION_TEST( 0x1, 1, 1, 0, 43 ) 
+        SV_PREDICATION_TEST( 0x0, 1, 1, 42, 43 ) 
+        SV_PREDICATION_TEST( 0x3, 1, 1, 0, 0 ) 
+*/
+
+        RVTEST_PASS           # Signal success.
+fail:
+        RVTEST_FAIL
+RVTEST_CODE_END     # End of test code.
+
+# Input data section.
+# This section is optional, and this data is NOT saved in the output.
+.data
+        .align 3
+testdata:
+        .dword 1001
+        .dword 0x4100000042
+        .dword 0x4300000044
+        .dword 1002
+
+# Output data section.
+RVTEST_DATA_BEGIN   # Start of test output data region.
+        .align 3
+result:
+        .dword -1
+        .dword -1
+        .dword -1
+RVTEST_DATA_END     # End of test output data region.
+