X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Frv64uv%2Ffmovn.S;h=44423701145f577bbb7d0978dbfadab34823e287;hb=f99d03cb43d8350dd35672cd9e1b872628882727;hp=a943326c5086eff00a4001993f3c70db4c4c12b2;hpb=57f2254feaf4e3595a5b6cce48ebcfbebaaa3c67;p=riscv-tests.git

diff --git a/isa/rv64uv/fmovn.S b/isa/rv64uv/fmovn.S
index a943326..4442370 100644
--- a/isa/rv64uv/fmovn.S
+++ b/isa/rv64uv/fmovn.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # fmovn.S
 #-----------------------------------------------------------------------------
@@ -8,7 +10,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,2
@@ -29,7 +31,7 @@ loop:
   slli a4,a4,63
   srai a4,a4,63
   and a5,a2,a4
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a5,fail
   addi a7,a7,8
   addi a1,a1,1