X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Frv64uv%2Fimul.S;h=ebfb77d0cb68d40b7100129ddcf972ef3dc62fd1;hb=160bdaa323bc8f8e651f9f546822336cf17d92f5;hp=bb9b6a36c4215834ec28369a822358d7e540374b;hpb=81ad66f25ce4c15180e558696961bd8eaf967fea;p=riscv-tests.git

diff --git a/isa/rv64uv/imul.S b/isa/rv64uv/imul.S
index bb9b6a3..ebfb77d 100644
--- a/isa/rv64uv/imul.S
+++ b/isa/rv64uv/imul.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # imul.S
 #-----------------------------------------------------------------------------
@@ -8,11 +10,12 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
+  vsetcfg 3,0
   li a3,2048
-  vvcfgivl a3,a3,3,0
+  vsetvl a3,a3
 
   li a4,20
   li s0,2
@@ -44,17 +47,17 @@ RVTEST_CODE_BEGIN
 
   la a5,dest
   vsd vx1,a5
-  fence.v.l
+  fence
 
   li s2,40
-  li x28,2
+  li TESTNUM,2
   bne s1,s2,fail
 
   li a1,0
   li a2,0
 loop:
   ld a0,0(a5)
-  addi x28,a2,3
+  addi TESTNUM,a2,3
   bne a0,a1,fail
   addi a5,a5,8
   addi a1,a1,20