X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Frv64uv%2Fvvadd_fd.S;h=a9961afb7c0459f4424b54ffda10823260fc3409;hb=1e014a8528f0362eb02437ec7b1273ba21ee3ba9;hp=7b2ce98ea2e32898d2221b85a7e5ae7685a214d7;hpb=57f2254feaf4e3595a5b6cce48ebcfbebaaa3c67;p=riscv-tests.git

diff --git a/isa/rv64uv/vvadd_fd.S b/isa/rv64uv/vvadd_fd.S
index 7b2ce98..a9961af 100644
--- a/isa/rv64uv/vvadd_fd.S
+++ b/isa/rv64uv/vvadd_fd.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,32
@@ -24,19 +24,19 @@ RVTEST_CODE_BEGIN
   la a5,dest
   vfsd vf2,a5
   fence
-  la a5,result
+  la a6,result
   ld a1,0(a5)
-  ld a2,0(a5)
-  li x28,2
+  ld a2,0(a6)
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
   j pass