X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=kernel%2Fyosys.cc;h=2ec3dca0cffeda704d13141a25c81250b0b07e94;hb=f975cf39cbedbca0482109b7aa625570a3857ee6;hp=8190d89028eb4ca553932977adb992379558b047;hpb=cd92a974f4cf8d4db74d504c38e51ce043e02403;p=yosys.git diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 8190d8902..2ec3dca0c 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -45,8 +45,10 @@ # include # include # include -# include # include +# if !defined(YOSYS_DISABLE_SPAWN) +# include +# endif #endif #if !defined(_WIN32) && defined(YOSYS_ENABLE_GLOB) @@ -129,7 +131,7 @@ void yosys_banner() log(" | |\n"); log(" | yosys -- Yosys Open SYnthesis Suite |\n"); log(" | |\n"); - log(" | Copyright (C) 2012 - 2019 Clifford Wolf |\n"); + log(" | Copyright (C) 2012 - 2020 Claire Wolf |\n"); log(" | |\n"); log(" | Permission to use, copy, modify, and/or distribute this software for any |\n"); log(" | purpose with or without fee is hereby granted, provided that the above |\n"); @@ -336,6 +338,7 @@ bool patmatch(const char *pattern, const char *string) return false; } +#if !defined(YOSYS_DISABLE_SPAWN) int run_command(const std::string &command, std::function process_line) { if (!process_line) @@ -364,10 +367,16 @@ int run_command(const std::string &command, std::function 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0) command = "ilang"; + else if (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".cc") == 0) + command = "cxxrtl"; else if (filename.size() > 4 && filename.compare(filename.size()-4, std::string::npos, ".aig") == 0) command = "aiger"; else if (filename.size() > 5 && filename.compare(filename.size()-5, std::string::npos, ".blif") == 0) @@ -1094,30 +1115,29 @@ static char *readline_obj_generator(const char *text, int state) if (design->selected_active_module.empty()) { - for (auto &it : design->modules_) - if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); + for (auto mod : design->modules()) + if (RTLIL::unescape_id(mod->name).compare(0, len, text) == 0) + obj_names.push_back(strdup(log_id(mod->name))); } - else - if (design->modules_.count(design->selected_active_module) > 0) + else if (design->module(design->selected_active_module) != nullptr) { - RTLIL::Module *module = design->modules_.at(design->selected_active_module); + RTLIL::Module *module = design->module(design->selected_active_module); - for (auto &it : module->wires_) - if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); + for (auto w : module->wires()) + if (RTLIL::unescape_id(w->name).compare(0, len, text) == 0) + obj_names.push_back(strdup(log_id(w->name))); for (auto &it : module->memories) if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); + obj_names.push_back(strdup(log_id(it.first))); - for (auto &it : module->cells_) - if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); + for (auto cell : module->cells()) + if (RTLIL::unescape_id(cell->name).compare(0, len, text) == 0) + obj_names.push_back(strdup(log_id(cell->name))); for (auto &it : module->processes) if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0) - obj_names.push_back(strdup(RTLIL::id2cstr(it.first))); + obj_names.push_back(strdup(log_id(it.first))); } std::sort(obj_names.begin(), obj_names.end());