X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=lkcl.mdwn;h=49f329798149d5a749c377ac456a3a73ee2be305;hb=29aca3237588221e2608ee85592163a8d953fea2;hp=d79837aa6b693b03a683906e327af7a4bdf4da39;hpb=06088e99c179e88b9ad27d442c3a1b35e33d2439;p=libreriscv.git
diff --git a/lkcl.mdwn b/lkcl.mdwn
index d79837aa6..49f329798 100644
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -4,6 +4,8 @@ Lead dev and Project Coordinator for Libre-SOC.
* [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
* [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
+* readthedocs link
+*
# Status tracking
@@ -12,9 +14,36 @@ move things along from one stage to the next
## Currently working on
- Project Management
- -
- -
- -
+ - Partitioned Logic
+ - IEEE754 FP layout
+ - Partitioned Mux
+ - EUR 250
+ - better Partitioned eq (Assign)
+ - EUR 300
+ - Partitioned Cat
+ - EUR 250
+ - Partitioned Type 2 DSL
+ - EUR 1250
+ - Partitioned Logic docs
+ - XLEN-16 fails
+ - symbiflow shared with [[veera]]
+ - adapt ALU test cases
+ - DCT FFT documentation
+ - SVSTATE extended to 64 bit
+ - OpenPOWER simulator
+ - ISACaller basic FP
+ - SVP64 simulation
+ - SVSTATE DMI
+ - SVP64 PowerDecoder2
+ - https://bugs.libre-soc.org/show_bug.cgi?id=575
+ - 3D Custom instructions
+ - Partitioning Proof
+ - Data merging FSM
+ - EUR
+ - SV Spec
+ - ISAMux writeup
+ - Create HDL MMU
+ - PartitionedSignal Module
- 6600 scoreboard
- branch prediction research
- LDST buffer
@@ -31,26 +60,125 @@ move things along from one stage to the next
- RA=0 tests
- misc opcodes
- FU multiple tasks
- - Branch proof
- - EUR 400 shared 25% [[mnolan]] EUR 100
- - ALU proof
- - EUR 500 shared [[mnolan]] samuel, TBD split
- - mul bug
- - LD/ST cache-inhibit
+ - LD/ST cache-inhibit
- EUR 200
- - DMI to JTAG
- - EUR 250 (share with cole)
+ - data handling API
+ - Formal proof of decoder
+ - donated
+ - parent #198
+ - EUR 200
+ - parent #197
+ - MultiCompUnit (and Function Units) proof
+ - POWER9 ROTATE proof
+ - donated
+ - parent #195
+ - SVP64 test documentation
+
+## Completed but not yet submitted:
+ - create Power ISA test API
+ - EUR 1600
+ - EUR 800 shared with [[klehman]]
+ - EUR 800 shared with [[lkcl]]
+ - ISACaller supporting XLEN
+ - EUR 500 shared between:
+ - EUR 100 [[lkcl]]
+ - EUR 325 dmitry
+ - EUR 75 maciej
+ - SVP64 preliminary decode
+ - EUR 800
+ - mul bug
+ - div errors
+ - mul overflow incorrect
+ - ISACaller RADIX MMU
+ - EUR 800 shared between:
+ - EUR 500 [[lkcl]]
+ - EUR 300 [[tplaten]]
+ - SVP64 Draft 0.1
+ - EUR 5500 shared between:
+ - EUR 3850 lkcl
+ - EUR 1650 Others
+ - DCT and FFT REMAP
+ - EUR 1600
+ - Matrix REMAP tests
+ - EUR 600
+ - SVP64 generator
+ - EUR 500
+ - 3D MESA planning
- litex peripheral set
- - pin-package for 180nm ASIC
- ls180 reset review
+ - JTAG boot upload/init
+ - JTAG IO Boundary test
-## Completed but not yet submitted:
+
+ - Logic pipe
+ - EUR 150
+ - donated
+ - CR pipe
+ - EUR 200
+ - donated
+ - Branch pipe
+ - EUR 150
+ - donated
+ - ALU pipe
+ - EUR 200
+ - donated
+ - coriolis2 tutorial
+ - EUR 700
+ - (lip6.fr donated)
+ - multi-clock example
+ - (total EUR 400 25% donated by LIP6)
+ - EUR 100 lkcl
+ - SV Overview
+ - EUR 900
+ - shared with [[lxo]]
+ - AV Opcode documentation
+ - EUR 1100
+ - shared with lauri, jacob
+ - Cocotb simulation
+ - EUR 1250
+ - Shared 50% with Staf
+ - 4k SRAM
+ - EUR 300
+ - Shared with Staf, cole
+ - IORing
+ - EUR 450
+ - Shared with Staf
+ - PowerDecoder2 simplification
+ - HDL changes for coriolis2
+ - EUR 3000
+ - shared with Staf 50%
+ - ULX3S boot
+ - Project 2019-10-043 06dec2020 wishbone
+ - EUR (TBD)
+
+### Project 2019-10-029 14mar2020 coriolis2
+
+ - pin-package for 180nm ASIC
+ - (total EUR 100 shared 50% with staf)
+ - EUR 50 lkcl
+ - ls180 ioring and pads
+ - (total EUR 1500 shared 50% with LIP6)
+ - EUR 750 lkcl
+ - multi-clock example
+ - (total EUR 400 shared 75% with LIP6)
+ - EUR 300 lkcl
+
+### Project 2019-02-012 06dec2020 Core
+
+ - pipeline API continued
+ - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
+ - CORDIC
+ - EUR 750 donated
+ - LDST Dep Matrix
+ - EUR 1500
+
+### Project 2019-10-043 06dec2020 wishbone
- SPR pipe
- EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
- DEC/TB
- EUR 200
- - LD/ST sign-extend
+ - LD/ST sign-extend
- EUR 100
- wishbone downconverter
- EUR 200
@@ -62,35 +190,32 @@ move things along from one stage to the next
- EUR 450
- addme bug
- EUR 100
-
-donated:
-
- POWER Decoder
- - with [[lkcl]]
- - CORDIC
- -
- - functions needed for simulator
- - Shared 90% with [[lkcl]]
- - parent #198
- - Formal proof of decoder
- - EUR 200
- - parent #195
- - POWER9 ALU proof
- - parent #195
- - POWER9 CR proof
- - parent #195
- - POWER9 BRANCH proof
- - parent #195
- - POWER9 LOGICAL proof
- - parent #195
- - POWER9 ROTATE proof
- - parent #197
- - MultiCompUnit (and Function Units) proof
+ - EUR 200 donated
+ - DMI to JTAG
+ - EUR 250 (share with cole)
+
+### Project 2019-10-032 06dec2020 proofs
+
+ - POWER9 ALU proof
+ - parent #195
+ - EUR 400 donated
+ - POWER9 CR proof
+ - parent #195
+ - EUR 300 donated
+ - POWER9 BRANCH proof
+ - EUR 400 donated
+ - parent #195
+ - POWER9 LOGICAL proof
+ - EUR 400 donated
+ - parent #195
## Submitted for NLNet RFP
submitted but not confirmed paid:
+ - HDL changes for coriolis2
+
### Project 2019-02-012 04sep2020 Core
- litex
@@ -111,7 +236,7 @@ donation from NLNet confirmed received:
- EUR 250, functions needed for simulator
- Shared 20% with [[mnolan]], EUR 50
-#### proofs 2019-10-032
+### proofs 2019-10-032
- Trap proof
- EUR 500 shared 20% samuel, EUR 100
@@ -188,7 +313,8 @@ donation from NLNet confirmed received:
### Project 2019-10-029 Date 14mar2020
-* coriolis2 start/tutorial EUR 1200
+* coriolis2 start/tutorial
+ - EUR 1200
### Project 2019-02-012 Date 12mar2020