X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=lkcl.mdwn;h=5f9a3262c795a3bad28da0e960cb5f376e81554f;hb=3ac854a88fa91660f63692b7b3a69cdc7dae7acc;hp=85cd73a97e8be97e5573dd4d3a0d6f04e27cf5c2;hpb=1cdec3eb4bc3de5bb8c0201fa01b6d039dff7b83;p=libreriscv.git diff --git a/lkcl.mdwn b/lkcl.mdwn index 85cd73a97..5f9a3262c 100644 --- a/lkcl.mdwn +++ b/lkcl.mdwn @@ -12,11 +12,23 @@ move things along from one stage to the next ## Currently working on - Project Management - - DEC/TB - - EUR 250 + - SVP64 PowerDecoder2 + - https://bugs.libre-soc.org/show_bug.cgi?id=575 + - 3D Custom instructions + - Partitioning Proof + - AV Opcode documrntation + - EUR + - Data merging FSM + - EUR + - SV Overview + - SV Spec + - ISAMux writeup + - HDL changes for coriolis2 - + - 3D MESA planning - - + - PartitionedSignal Module - 6600 scoreboard - branch prediction research - LDST buffer @@ -27,23 +39,65 @@ move things along from one stage to the next - DIV proof - SHIFTROT proof - Compunit RA=0 test - - SPR pipe - SPR proof + - EUR 50, shared with samuel (EUR 350) - LDST RA=0 test - RA=0 tests - misc opcodes - FU multiple tasks - - Branch proof - - EUR 400 shared 25% [[mnolan]] EUR 100 - - ALU proof - - EUR 500 shared [[mnolan]] samuel, TBD split - mul bug - - LD/ST cache-inhibit + - LD/ST cache-inhibit + - EUR 200 + - litex peripheral set + - ls180 reset review + - JTAG boot upload/init + - JTAG IO Boundary test + - data handling API + - Formal proof of decoder + - donated + - parent #198 - EUR 200 + - parent #197 + - MultiCompUnit (and Function Units) proof + - POWER9 ROTATE proof + - donated + - parent #195 ## Completed but not yet submitted: - - LD/ST sign-extend + - PowerDecoder2 simplification + - ULX3S boot + - Project 2019-10-043 06dec2020 wishbone + - EUR 0 (TBD) + +### Project 2019-10-029 14mar2020 coriolis2 + + - pin-package for 180nm ASIC + - (total EUR 100 shared 50% with staf) + - EUR 50 lkcl + - ls180 ioring and pads + - (total EUR 1500 shared 50% with LIP6) + - EUR 750 lkcl + - multi-clock example + - (total EUR 400 shared 75% with LIP6) + - EUR 300 lkcl + +### Project 2019-02-012 06dec2020 Core + + - pipeline API continued + - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200 + - CORDIC + - EUR 750 donated + - LDST Dep Matrix + - EUR 1500 + +### Project 2019-10-043 06dec2020 wishbone + + - SPR pipe + - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300 + - DEC/TB + - EUR 200 + - LD/ST sign-extend - EUR 100 - wishbone downconverter - EUR 200 @@ -55,6 +109,25 @@ move things along from one stage to the next - EUR 450 - addme bug - EUR 100 + - POWER Decoder + - EUR 200 donated + - DMI to JTAG + - EUR 250 (share with cole) + +### Project 2019-10-032 06dec2020 proofs + + - POWER9 ALU proof + - parent #195 + - EUR 400 donated + - POWER9 CR proof + - parent #195 + - EUR 300 donated + - POWER9 BRANCH proof + - EUR 400 donated + - parent #195 + - POWER9 LOGICAL proof + - EUR 400 donated + - parent #195 ## Submitted for NLNet RFP @@ -80,7 +153,7 @@ donation from NLNet confirmed received: - EUR 250, functions needed for simulator - Shared 20% with [[mnolan]], EUR 50 -#### proofs 2019-10-032 +### proofs 2019-10-032 - Trap proof - EUR 500 shared 20% samuel, EUR 100 @@ -157,7 +230,8 @@ donation from NLNet confirmed received: ### Project 2019-10-029 Date 14mar2020 -* coriolis2 start/tutorial EUR 1200 +* coriolis2 start/tutorial + - EUR 1200 ### Project 2019-02-012 Date 12mar2020