X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=lkcl.mdwn;h=9dbc3a1220924c9a2eacacfee3a94b1abcd13c53;hb=33e54cae365c747e4117886badc9b12731c40887;hp=34aeab790e321e72404ec9a73c8294821bcd19dc;hpb=f70fa8f6cc1f3c1baf487e4ae80b9789f586ff4d;p=libreriscv.git

diff --git a/lkcl.mdwn b/lkcl.mdwn
index 34aeab790..9dbc3a122 100644
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -25,7 +25,6 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
- - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
  - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
@@ -42,6 +41,7 @@ move things along from one stage to the next
 
 ## Completed but not yet submitted:
 
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
  - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
  - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
  - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof