X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=lkcl.mdwn;h=abe5fbddff78f27bbfb099797912cb85e5c73c5b;hb=ac15bdcda4ac1d85489ff8fb286064039cb3ba84;hp=75ad24f6077cd9699f547a633ce56dcc926f4798;hpb=bcc625187df5eb9c280bf83bd343d3c8fbc9403a;p=libreriscv.git
diff --git a/lkcl.mdwn b/lkcl.mdwn
index 75ad24f60..abe5fbddf 100644
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -4,6 +4,8 @@ Lead dev and Project Coordinator for Libre-SOC.
* [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
* [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
+* readthedocs link
+*
# Status tracking
@@ -12,6 +14,30 @@ move things along from one stage to the next
## Currently working on
- Project Management
+ - binutils magic
+ - SVP64 whitepaper
+ - Documentation SVP64 Proposals
+ - management, binutils
+ - donated, Simulator
+ - SV Encoding
+ - nextpnr-xilinx
+ - EUR 150
+ - ls2 documentation
+ - EUR 150
+ - SVP64 Branches
+ - EUR 1000
+ - Partitioned Logic
+ - Partitioned Mux
+ - EUR 250
+ - Partitioned Type 2 DSL
+ - EUR 1250
+ - Partitioned Logic docs
+ - XLEN-16 fails
+ - DCT FFT documentation
+ - SVSTATE extended to 64 bit
+ - OpenPOWER simulator
+ - ISACaller basic FP
+ - SVP64 simulation
- SVSTATE DMI
- SVP64 PowerDecoder2
- https://bugs.libre-soc.org/show_bug.cgi?id=575
@@ -19,14 +45,9 @@ move things along from one stage to the next
- Partitioning Proof
- Data merging FSM
- EUR
- - SV Overview
- SV Spec
- ISAMux writeup
- - HDL changes for coriolis2
- -
- - 3D MESA planning
- -
- -
+ - Create HDL MMU
- PartitionedSignal Module
- 6600 scoreboard
- branch prediction research
@@ -36,7 +57,7 @@ move things along from one stage to the next
- MUL proof
- EUR 50, shared with samuel 10%
- DIV proof
- - SHIFTROT proof
+
- Compunit RA=0 test
- SPR proof
- EUR 50, shared with samuel (EUR 350)
@@ -44,13 +65,8 @@ move things along from one stage to the next
- RA=0 tests
- misc opcodes
- FU multiple tasks
- - mul bug
- LD/ST cache-inhibit
- EUR 200
- - litex peripheral set
- - ls180 reset review
- - JTAG boot upload/init
- - JTAG IO Boundary test
- data handling API
- Formal proof of decoder
- donated
@@ -61,22 +77,79 @@ move things along from one stage to the next
- POWER9 ROTATE proof
- donated
- parent #195
+ - SVP64 test documentation
## Completed but not yet submitted:
+TO SORT
+
+28feb2022
+
+ - icache
+ * EUR 1500 (shared with [[tplaten]])
+ - dcache
+ * EUR 1500 (shared with [[tplaten]])
+ - mmu
+ * EUR 1000 (shared with [[tplaten]])
+ - MUL Formal (donated)
+ * EUR 500 (shared with [[programmerjake]])
+ - SHIFTROT proof
+ * EUR 400 (shared with [[programmerjake]])
+
+before that
+
+ - create Power ISA test API
+ - EUR 1600
+ - EUR 800 shared with [[klehman]]
+ - EUR 800 shared with [[lkcl]]
+ - SVP64 preliminary decode
+ - EUR 800
+ - mul bug
+ - div errors
+ - mul overflow incorrect
+ - SVP64 generator
+ - EUR 500
+ - 3D MESA planning
+ - litex peripheral set
+ - ls180 reset review
+ - JTAG boot upload/init
+ - JTAG IO Boundary test
+
+
+ - Logic pipe
+ - EUR 150
+ - donated
+ - CR pipe
+ - EUR 200
+ - donated
+ - Branch pipe
+ - EUR 150
+ - donated
+ - ALU pipe
+ - EUR 200
+ - donated
+ - coriolis2 tutorial
+ - EUR 700
+ - (lip6.fr donated)
+ - multi-clock example
+ - (total EUR 400 25% donated by LIP6)
+ - EUR 100 lkcl
+ - SV Overview
+ - EUR 900
+ - shared with [[lxo]]
- AV Opcode documentation
- EUR 1100
- shared with lauri, jacob
-- Cocotb simulation
+ - Cocotb simulation
- EUR 1250
- Shared 50% with Staf
-- 4k SRAM
- - EUR TBD
+ - 4k SRAM
+ - EUR 300
+ - Shared with Staf, cole
+ - IORing
+ - EUR 450
- Shared with Staf
- PowerDecoder2 simplification
- - HDL changes for coriolis2
- - EUR 3000
- - shared with Staf 50%
- ULX3S boot
- Project 2019-10-043 06dec2020 wishbone
- EUR (TBD)
@@ -142,7 +215,33 @@ move things along from one stage to the next
## Submitted for NLNet RFP
-submitted but not confirmed paid:
+submitted 2021-dec-09 but not confirmed paid
+
+ - better Partitioned eq (Assign)
+ - EUR 300
+ - Partitioned Cat
+ - EUR 250
+ - IEEE754 FP layout
+ - symbiflow shared with [[veera]]
+ - ISACaller RADIX MMU
+ - EUR 800 shared between:
+ - EUR 500 [[lkcl]]
+ - EUR 300 [[tplaten]]
+ - SVP64 Draft 0.1
+ - EUR 5500 shared between:
+ - EUR 3850 lkcl
+ - EUR 1650 Others
+ - DCT and FFT REMAP
+ - EUR 1600
+ - Matrix REMAP tests
+ - EUR 600
+ - ISACaller supporting XLEN
+ - EUR 500 shared between:
+ - EUR 100 [[lkcl]]
+ - EUR 325 dmitry
+ - EUR 75 maciej
+ - adapt ALU test cases
+
### Project 2019-02-012 04sep2020 Core
@@ -155,6 +254,12 @@ submitted but not confirmed paid:
donation from NLNet confirmed received:
+### coriolis2 2021-apr-04
+
+ - HDL changes for coriolis2
+ - EUR 3000
+ - shared with Staf 50%
+
### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
-