X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=lkcl.mdwn;h=c7f06f0d9a6a90c55371f036aa3a181dc25a985f;hb=a175a4756f5b4e1350d2099c3f0aae4954b337ed;hp=e561bda7abc218cc6a0c7b3c8e5dd27aca512928;hpb=c172e4b88f474a0b4e538ae0b55c497695490350;p=libreriscv.git
diff --git a/lkcl.mdwn b/lkcl.mdwn
index e561bda7a..c7f06f0d9 100644
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -6,6 +6,12 @@ Lead dev and Project Coordinator for Libre-SOC.
* [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
* readthedocs link
*
+*
+
+# Priority tasks to keep an eye on
+
+* 6600 proof
+ EUR 5000
# Status tracking
@@ -14,8 +20,36 @@ move things along from one stage to the next
## Currently working on
- Project Management
+ - PartitionedSignal RFC
+ - EUR 1500
+ - nmigen c compiler
+ - ISANS letter
+ - ISA switch
+ - Compressed writeup
+ - SVP64 Primer
+ - svindex
+ - binutils draft instructions
+ - cr int draft instructions
+ - 3D MESA
+ - binutils magic
+ - SVP64 whitepaper
+ - Documentation SVP64 Proposals
+ - management, binutils
+ - donated, Simulator
+ - SV Encoding
+ - nextpnr-xilinx
+ - EUR 150
+ - ls2 documentation
+ - EUR 150
+ - SVP64 Branches
+ - EUR 1000
+ - Partitioned Logic
+ - Partitioned Mux
+ - EUR 250
+ - Partitioned Type 2 DSL
+ - EUR 1000 of 1250 shared
+ - Partitioned Logic docs
- XLEN-16 fails
- - symbiflow shared with [[veera]]
- DCT FFT documentation
- SVSTATE extended to 64 bit
- OpenPOWER simulator
@@ -31,7 +65,6 @@ move things along from one stage to the next
- SV Spec
- ISAMux writeup
- Create HDL MMU
- - PartitionedSignal Module
- 6600 scoreboard
- branch prediction research
- LDST buffer
@@ -40,7 +73,7 @@ move things along from one stage to the next
- MUL proof
- EUR 50, shared with samuel 10%
- DIV proof
- - SHIFTROT proof
+
- Compunit RA=0 test
- SPR proof
- EUR 50, shared with samuel (EUR 350)
@@ -63,28 +96,33 @@ move things along from one stage to the next
- SVP64 test documentation
## Completed but not yet submitted:
- - ISACaller supporting XLEN
- - EUR 500 shared between:
- - EUR 100 [[lkcl]]
- - EUR 325 dmitry
- - EUR 75 maciej
+
+TO SORT
+
+28feb2022
+
+ - icache
+ * EUR 1500 (shared with [[tplaten]])
+ - dcache
+ * EUR 1500 (shared with [[tplaten]])
+ - mmu
+ * EUR 1000 (shared with [[tplaten]])
+ - MUL Formal (donated)
+ * EUR 500 (shared with [[programmerjake]])
+ - SHIFTROT proof
+ * EUR 400 (shared with [[programmerjake]])
+
+before that
+
+ - create Power ISA test API
+ - EUR 1600
+ - EUR 800 shared with [[klehman]]
+ - EUR 800 shared with [[lkcl]]
- SVP64 preliminary decode
- EUR 800
- mul bug
- div errors
- mul overflow incorrect
- - ISACaller RADIX MMU
- - EUR 800 shared between:
- - EUR 500 [[lkcl]]
- - EUR 300 [[tplaten]]
- - SVP64 Draft 0.1
- - EUR 5500 shared between:
- - EUR 3850 lkcl
- - EUR 1650 Others
- - DCT and FFT REMAP
- - EUR 1600
- - Matrix REMAP tests
- - EUR 600
- SVP64 generator
- EUR 500
- 3D MESA planning
@@ -128,9 +166,6 @@ move things along from one stage to the next
- EUR 450
- Shared with Staf
- PowerDecoder2 simplification
- - HDL changes for coriolis2
- - EUR 3000
- - shared with Staf 50%
- ULX3S boot
- Project 2019-10-043 06dec2020 wishbone
- EUR (TBD)
@@ -196,9 +231,33 @@ move things along from one stage to the next
## Submitted for NLNet RFP
-submitted but not confirmed paid:
+submitted 2021-dec-09 but not confirmed paid
+
+ - better Partitioned eq (Assign)
+ - EUR 300
+ - Partitioned Cat
+ - EUR 250
+ - IEEE754 FP layout
+ - symbiflow shared with [[veera]]
+ - ISACaller RADIX MMU
+ - EUR 800 shared between:
+ - EUR 500 [[lkcl]]
+ - EUR 300 [[tplaten]]
+ - SVP64 Draft 0.1
+ - EUR 5500 shared between:
+ - EUR 3850 lkcl
+ - EUR 1650 Others
+ - DCT and FFT REMAP
+ - EUR 1600
+ - Matrix REMAP tests
+ - EUR 600
+ - ISACaller supporting XLEN
+ - EUR 500 shared between:
+ - EUR 100 [[lkcl]]
+ - EUR 325 dmitry
+ - EUR 75 maciej
+ - adapt ALU test cases
- - HDL changes for coriolis2
### Project 2019-02-012 04sep2020 Core
@@ -211,6 +270,12 @@ submitted but not confirmed paid:
donation from NLNet confirmed received:
+### coriolis2 2021-apr-04
+
+ - HDL changes for coriolis2
+ - EUR 3000
+ - shared with Staf 50%
+
### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
-