X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=lkcl.mdwn;h=c7f06f0d9a6a90c55371f036aa3a181dc25a985f;hb=b1331f37e6b41ac133f4286486a4af27b3f7fc1a;hp=a35752b81e01aba2dd6605d76558c62514b2da59;hpb=fd4a9e7bb7be36c2633ad1c568d199f3555305be;p=libreriscv.git

diff --git a/lkcl.mdwn b/lkcl.mdwn
index a35752b81..c7f06f0d9 100644
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -4,6 +4,14 @@ Lead dev and Project Coordinator for Libre-SOC.
 
 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
+* <https://readthedocs.org/profiles/lkcl/> readthedocs link
+* <http://twitter.com/lkcl>
+* <https://libre-soc.org/task_db/>
+
+# Priority tasks to keep an eye on
+
+* <https://bugs.libre-soc.org/show_bug.cgi?id=197> 6600 proof
+  EUR 5000
 
 # Status tracking
 
@@ -12,6 +20,41 @@ move things along from one stage to the next
 ## Currently working on
 
  - Project Management
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=594> PartitionedSignal RFC
+   - EUR 1500
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=665> nmigen c compiler
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISANS letter
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=240> ISA switch
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=238> Compressed writeup
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=858> SVP64 Primer
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=867> svindex
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=834> binutils draft instructions
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=533> cr int draft instructions
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=251> 3D MESA
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=844> binutils magic
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=839> SVP64 whitepaper
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=243> Documentation SVP64 Proposals
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=834> management, binutils
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=463> donated, Simulator
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=790> nextpnr-xilinx
+   - EUR 150
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=802> ls2 documentation
+   - EUR 150
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
+   - EUR 1000
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
+   - EUR 250
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
+   - EUR 1000 of 1250 shared
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  - https://bugs.libre-soc.org/show_bug.cgi?id=575
@@ -21,12 +64,7 @@ move things along from one stage to the next
    - EUR 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
- - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
- - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
- - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
- - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
- - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
- - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
  - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
  - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
  - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
@@ -35,7 +73,7 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
    - EUR 50, shared with samuel 10%
  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
- - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
+
  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
    - EUR 50, shared with samuel (EUR 350)
@@ -43,13 +81,8 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
  - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
  - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
- - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
    - EUR 200
- - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
- - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
- - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
- - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
    - donated
@@ -60,9 +93,45 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
   - donated
   - parent #195
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation 
 
 ## Completed but not yet submitted:
 
+TO SORT
+
+28feb2022
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
+   * EUR 1500 (shared with [[tplaten]])
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
+   * EUR 1500 (shared with [[tplaten]])
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
+   * EUR 1000 (shared with [[tplaten]])
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
+   * EUR 500 (shared with [[programmerjake]])
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
+   * EUR 400 (shared with [[programmerjake]])
+
+before that
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
+   - EUR 1600
+   - EUR 800 shared with [[klehman]]
+   - EUR 800 shared with [[lkcl]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
+   - EUR 800
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
+   - EUR 500
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
+
+
  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
    - EUR 150
    - donated
@@ -97,9 +166,6 @@ move things along from one stage to the next
    - EUR 450
    - Shared with Staf
  - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
- - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
-   - EUR 3000
-   - shared with Staf 50%
  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
    - Project 2019-10-043 06dec2020 wishbone
    - EUR (TBD)
@@ -165,7 +231,33 @@ move things along from one stage to the next
 
 ## Submitted for NLNet RFP
 
-submitted but not confirmed paid:
+submitted 2021-dec-09 but not confirmed paid
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
+   - EUR 300
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
+   - EUR 250
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
+   - EUR 800 shared between:
+   - EUR 500 [[lkcl]]
+   - EUR 300 [[tplaten]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
+   - EUR 5500 shared between:
+   - EUR 3850 lkcl
+   - EUR 1650 Others
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
+   - EUR 1600
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
+   - EUR 600
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
+   - EUR 500 shared between:
+   - EUR 100 [[lkcl]]
+   - EUR 325 dmitry
+   - EUR 75 maciej
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
+
 
 ### Project 2019-02-012 04sep2020 Core
 
@@ -178,6 +270,12 @@ submitted but not confirmed paid:
 
 donation from NLNet confirmed received:
 
+### coriolis2 2021-apr-04
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
+   - EUR 3000
+   - shared with Staf 50%
+
 ### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER 
 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=463>