X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=lkcl.mdwn;h=d6fd0cfadd94c880d7ba64f2b8a24dfbe2992717;hb=057c91119e5fae4f6ae667dd3b191a8a27fee490;hp=a326e566669341f747bd7ad290bca7b5b11f89a6;hpb=9e6789ca9d659450d354bb74786c0a7ab5a70ebf;p=libreriscv.git
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Lead dev and Project Coordinator for Libre-SOC.
+* [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
+* [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
+* readthedocs link
+*
+
# Status tracking
move things along from one stage to the next
## Currently working on
-* Project Management
-* simd partitioned signal
-* coriolis2 start/tutorial
+ - Project Management
+ - Partitioned Logic
+ - Partitioned Mux
+ - EUR 250
+ - better Partitioned eq (Assign)
+ - EUR 300
+ - Partitioned Cat
+ - EUR 250
+ - Partitioned Type 2 DSL
+ - EUR 1250
+ - Partitioned Logic docs
+ - XLEN-16 fails
+ - symbiflow shared with [[veera]]
+ - DCT FFT documentation
+ - SVSTATE extended to 64 bit
+ - OpenPOWER simulator
+ - ISACaller basic FP
+ - SVP64 simulation
+ - SVSTATE DMI
+ - SVP64 PowerDecoder2
+ - https://bugs.libre-soc.org/show_bug.cgi?id=575
+ - 3D Custom instructions
+ - Partitioning Proof
+ - Data merging FSM
+ - EUR
+ - SV Spec
+ - ISAMux writeup
+ - Create HDL MMU
+ - PartitionedSignal Module
+ - 6600 scoreboard
+ - branch prediction research
+ - LDST buffer
+ - MUL tests
+ - shared with cole
+ - MUL proof
+ - EUR 50, shared with samuel 10%
+ - DIV proof
+ - SHIFTROT proof
+ - Compunit RA=0 test
+ - SPR proof
+ - EUR 50, shared with samuel (EUR 350)
+ - LDST RA=0 test
+ - RA=0 tests
+ - misc opcodes
+ - FU multiple tasks
+ - LD/ST cache-inhibit
+ - EUR 200
+ - data handling API
+ - Formal proof of decoder
+ - donated
+ - parent #198
+ - EUR 200
+ - parent #197
+ - MultiCompUnit (and Function Units) proof
+ - POWER9 ROTATE proof
+ - donated
+ - parent #195
+ - SVP64 test documentation
## Completed but not yet submitted:
+ - create Power ISA test API
+ - EUR 1600
+ - EUR 800 shared with [[klehman]]
+ - EUR 800 shared with [[lkcl]]
+ - ISACaller supporting XLEN
+ - EUR 500 shared between:
+ - EUR 100 [[lkcl]]
+ - EUR 325 dmitry
+ - EUR 75 maciej
+ - SVP64 preliminary decode
+ - EUR 800
+ - mul bug
+ - div errors
+ - mul overflow incorrect
+ - ISACaller RADIX MMU
+ - EUR 800 shared between:
+ - EUR 500 [[lkcl]]
+ - EUR 300 [[tplaten]]
+ - SVP64 Draft 0.1
+ - EUR 5500 shared between:
+ - EUR 3850 lkcl
+ - EUR 1650 Others
+ - DCT and FFT REMAP
+ - EUR 1600
+ - Matrix REMAP tests
+ - EUR 600
+ - SVP64 generator
+ - EUR 500
+ - 3D MESA planning
+ - litex peripheral set
+ - ls180 reset review
+ - JTAG boot upload/init
+ - JTAG IO Boundary test
+
+
+ - Logic pipe
+ - EUR 150
+ - donated
+ - CR pipe
+ - EUR 200
+ - donated
+ - Branch pipe
+ - EUR 150
+ - donated
+ - ALU pipe
+ - EUR 200
+ - donated
+ - coriolis2 tutorial
+ - EUR 700
+ - (lip6.fr donated)
+ - multi-clock example
+ - (total EUR 400 25% donated by LIP6)
+ - EUR 100 lkcl
+ - SV Overview
+ - EUR 900
+ - shared with [[lxo]]
+ - AV Opcode documentation
+ - EUR 1100
+ - shared with lauri, jacob
+ - Cocotb simulation
+ - EUR 1250
+ - Shared 50% with Staf
+ - 4k SRAM
+ - EUR 300
+ - Shared with Staf, cole
+ - IORing
+ - EUR 450
+ - Shared with Staf
+ - PowerDecoder2 simplification
+ - HDL changes for coriolis2
+ - EUR 3000
+ - shared with Staf 50%
+ - ULX3S boot
+ - Project 2019-10-043 06dec2020 wishbone
+ - EUR (TBD)
+
+### Project 2019-10-029 14mar2020 coriolis2
+
+ - pin-package for 180nm ASIC
+ - (total EUR 100 shared 50% with staf)
+ - EUR 50 lkcl
+ - ls180 ioring and pads
+ - (total EUR 1500 shared 50% with LIP6)
+ - EUR 750 lkcl
+ - multi-clock example
+ - (total EUR 400 shared 75% with LIP6)
+ - EUR 300 lkcl
+
+### Project 2019-02-012 06dec2020 Core
+
+ - pipeline API continued
+ - EUR 700 lkcl, EUR 500 [[programmerjake]], total EUR 1200
+ - CORDIC
+ - EUR 750 donated
+ - LDST Dep Matrix
+ - EUR 1500
+
+### Project 2019-10-043 06dec2020 wishbone
-* fcvt range
-* dynamic shift
+ - SPR pipe
+ - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
+ - DEC/TB
+ - EUR 200
+ - LD/ST sign-extend
+ - EUR 100
+ - wishbone downconverter
+ - EUR 200
+ - privileged detection
+ - EUR 100
+ - mfcr FXM
+ - EUR 200
+ - XICS
+ - EUR 450
+ - addme bug
+ - EUR 100
+ - POWER Decoder
+ - EUR 200 donated
+ - DMI to JTAG
+ - EUR 250 (share with cole)
+
+### Project 2019-10-032 06dec2020 proofs
+
+ - POWER9 ALU proof
+ - parent #195
+ - EUR 400 donated
+ - POWER9 CR proof
+ - parent #195
+ - EUR 300 donated
+ - POWER9 BRANCH proof
+ - EUR 400 donated
+ - parent #195
+ - POWER9 LOGICAL proof
+ - EUR 400 donated
+ - parent #195
## Submitted for NLNet RFP
submitted but not confirmed paid:
-### Project 2019-02-012 Date 28jan2020
+ - HDL changes for coriolis2
-* admin tasks
-*
+### Project 2019-02-012 04sep2020 Core
+
+ - litex
+ - EUR 2000 total, shared with florent. EUR 1200
+
+### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
## Paid
donation from NLNet confirmed received:
+### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
+
+ -
+ - EUR 2000, python POWER9 simulator
+ - Shared 50% with [[mnolan]], EUR 1000
+ -
+ - EUR 250, functions needed for simulator
+ - Shared 20% with [[mnolan]], EUR 50
+
+### proofs 2019-10-032
+
+ - Trap proof
+ - EUR 500 shared 20% samuel, EUR 100
+ - CR proof
+ - EUR 300 shared 1/6 [[mnolan]] EUR 50
+ - Logic proof
+ - EUR 400 shared 25% [[mnolan]] EUR 100
+ - countzero proof
+ - EUR 150
+
+### wishbone 2019-10-043
+
+ - Document 6600
+ - EUR 500
+ - WB to LDST
+ - EUR 300
+ - DMI interface
+ - EUR 250
+ - opcode decoder
+ - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
+ - SHIFTROT pipe
+ - EUR 300
+ - test improvement
+ - EUR 400, 50% shared [[programmerjake]] EUR 200
+ - MUL pipe
+ - EUR 750, 33% shared [[programmerjake]] EUR 250
+ - virtual regfile port
+ - EUR 200 50% shared, cole, EUR 100
+ - POWER9 regfiles
+ - EUR 200
+ - Trap pipe
+ - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
+ - SRAM wishbone object
+ - EUR 150
+ - ALU pipe
+ - EUR 400 shared 50% [[mnolan]] EUR 200
+ - Branch pipe
+ - EUR 250 shared 40% [[mnolan]] EUR 100
+ - CR pipe
+ - EUR 300 shared 1/3 [[mnolan]] EUR 100
+ - Logic pipe
+ - EUR 300 shared 50% [[mnolan]] EUR 150
+ - regfile-core
+ - EUR 750
+ - add mtmsrd
+ - EUR 100
+ - illegal instructions
+ - EUR 100
+ - MSR and PC "state"
+ - EUR 100
+ - DIV pipe
+ - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
+
+### Project 2019-02-012 28-apr-2020
+
+ -
+ - 6600 scoreboard multi-read/write
+ - EUR 600
+ - parent #48
+ - Partitioned equals and greater than comparison
+ - Shared 50% with [[mnolan]]
+ - EUR 200 (each)
+ - parent #48
+ - partitioned scalar/vector shift
+ - Shared 50% with [[lkcl]]
+ - EUR 350 (each)
+
+### 2019-10P-046 28-apr-2020 NLNet 2019 Formal Standards OpenPOWER
+
+ - parent #241
+ - auto-parser of POWER9
+ - Shared 50% with [[mnolan]]
+ - EUR 500 (each)
+
+### Project 2019-10-029 Date 14mar2020
+
+* coriolis2 start/tutorial
+ - EUR 1200
+
+### Project 2019-02-012 Date 12mar2020
+
+* fcvt range 100% EUR 250
+* 50% with [[mnolan]] EUR 200
+* dynamic shift 50% with [[mnolan]] EUR 350
+* EUR 900 shared with [[programmerjake]]
+
+### Project 2019-02-012 Date 28jan2020
+
+* admin tasks
+*
+