X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=llvm_vector_backend.mdwn;h=4f1db0f16b0c808f877d76f1f0fcaf651a0904c5;hb=ffb4ef6dd387ed85aa36b6c33c7a4187145d84c0;hp=2393082d7f2741a2dbada0ba85208733bb655f95;hpb=03dbf9de756a6e3325432b10440db1a1dc305f80;p=libreriscv.git

diff --git a/llvm_vector_backend.mdwn b/llvm_vector_backend.mdwn
index 2393082d7..4f1db0f16 100644
--- a/llvm_vector_backend.mdwn
+++ b/llvm_vector_backend.mdwn
@@ -1,5 +1,18 @@
 # LLVM Backend Array Register Files
 
+This backend is for expressing scenarios where registers have multiple
+potential overlapping meanings and uses, including but not limited to:
+
+* **MMX / SSE / SIMD**: same registers of fixed length can be subdivided into
+  multiple different SIMD elements, depending on the opcode used (or
+  special CSRs - Control Status Registers)
+* **Virtual register redirection**: setting a CSR changes
+  the meaning of instruction opcodes to access different "banks".
+* **Special register types**: expression of special register types,
+  not just integer and float, but shader types for use in 3D, or
+  Galois Field (GF).
+* Variations and combinations of the above
+
 # Data Structures
 
 ## Array Register File
@@ -60,23 +73,17 @@ and uses to which registers may be put can be expressed in one structure.
 
 ### SimpleV
 
-### RVV
-
 ### AMDGPU
 
 ## Base Register Class
 
 ### SimpleV
 
-### RVV
-
 ### AMDGPU
 
 ## Register Class Unions
 
 ### SimpleV
 
-### RVV
-
 ### AMDGPU