X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=milkymist%2Fdvisampler%2F__init__.py;h=0f338fcecaa952843dc56980f50d255dc9dfe8cc;hb=515cdb2bd8c6c138e47c4b0f2776ea9a86299b12;hp=d20880a026f27af16bc20ef56f1c322ffa205051;hpb=7c4ca4fd66f2b9f60188b6ad42210e525df161c7;p=litex.git

diff --git a/milkymist/dvisampler/__init__.py b/milkymist/dvisampler/__init__.py
index d20880a0..0f338fce 100644
--- a/milkymist/dvisampler/__init__.py
+++ b/milkymist/dvisampler/__init__.py
@@ -5,6 +5,7 @@ from migen.bank.description import *
 from milkymist.dvisampler.edid import EDID
 from milkymist.dvisampler.clocking import Clocking
 from milkymist.dvisampler.datacapture import DataCapture
+from milkymist.dvisampler.charsync import CharSync
 
 class DVISampler(Module, AutoReg):
 	def __init__(self, inversions=""):
@@ -18,13 +19,18 @@ class DVISampler(Module, AutoReg):
 		for datan in "012":
 			name = "data" + str(datan)
 			invert = datan in inversions
+			
+			signame = name + "_n" if invert else name
+			s = Signal(name=signame)
+			setattr(self, signame, s)
+
 			cap = DataCapture(8, invert)
 			setattr(self.submodules, name + "_cap", cap)
-			if invert:
-				name += "_n"
-			s = Signal(name=name)
-			setattr(self, name, s)
 			self.comb += [
 				cap.pad.eq(s),
 				cap.serdesstrobe.eq(self.clocking.serdesstrobe)
 			]
+
+			charsync = CharSync()
+			setattr(self.submodules, name + "_charsync", charsync)
+			self.comb += charsync.raw_data.eq(cap.d)