X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=milkymist%2Fframebuffer%2F__init__.py;h=dff5817ae671fa58f33db49da2e7a19c8026836d;hb=91d7b656a9be99e0e7d3812f915f41af74c76440;hp=2f3cef1cb7c8ee8089410d005dd1f403932ec4f5;hpb=398679062121908a9806b622d5c12a86b4dbafbf;p=litex.git diff --git a/milkymist/framebuffer/__init__.py b/milkymist/framebuffer/__init__.py index 2f3cef1c..dff5817a 100644 --- a/milkymist/framebuffer/__init__.py +++ b/milkymist/framebuffer/__init__.py @@ -1,225 +1,132 @@ -from migen.fhdl.structure import * +from migen.fhdl.std import * from migen.flow.actor import * from migen.flow.network import * -from migen.flow import plumbing -from migen.actorlib import misc, dma_asmi, structuring, sim, spi -from migen.bank.description import * -from migen.bank import csrgen +from migen.bank.description import CSRStorage, AutoCSR +from migen.actorlib import dma_lasmi, structuring, sim, spi -_hbits = 11 -_vbits = 11 +from milkymist.framebuffer.lib import bpp, pixel_layout, dac_layout, FrameInitiator, VTG, FIFO -_bpp = 32 -_bpc = 10 -_pixel_layout = [ - ("b", _bpc), - ("g", _bpc), - ("r", _bpc), - ("pad", _bpp-3*_bpc) -] - -_bpc_dac = 8 -_dac_layout = [ - ("hsync", 1), - ("vsync", 1), - ("b", _bpc_dac), - ("g", _bpc_dac), - ("r", _bpc_dac) -] - -class _FrameInitiator(spi.SingleGenerator): - def __init__(self, asmi_bits, length_bits, alignment_bits): - layout = [ - ("hres", _hbits, 640), - ("hsync_start", _hbits, 656), - ("hsync_end", _hbits, 752), - ("hscan", _hbits, 799), - - ("vres", _vbits, 480), - ("vsync_start", _vbits, 492), - ("vsync_end", _vbits, 494), - ("vscan", _vbits, 524), - - ("base", asmi_bits, 0, alignment_bits), - ("length", length_bits, 640*480*4, alignment_bits) - ] - super().__init__(layout, spi.MODE_CONTINUOUS) - -class VTG(Actor): - def __init__(self): - super().__init__( - ("timing", Sink, [ - ("hres", _hbits), - ("hsync_start", _hbits), - ("hsync_end", _hbits), - ("hscan", _hbits), - ("vres", _vbits), - ("vsync_start", _vbits), - ("vsync_end", _vbits), - ("vscan", _vbits)]), - ("pixels", Sink, _pixel_layout), - ("dac", Source, _dac_layout) - ) - - def get_fragment(self): - hactive = Signal() - vactive = Signal() - active = Signal() +class Framebuffer(Module): + def __init__(self, pads, lasmim, simulation=False): + pack_factor = lasmim.dw//(2*bpp) + packed_pixels = structuring.pack_layout(pixel_layout, pack_factor) - generate_en = Signal() - hcounter = Signal(_hbits) - vcounter = Signal(_vbits) + fi = FrameInitiator() + dma = spi.DMAReadController(dma_lasmi.Reader(lasmim), spi.MODE_EXTERNAL, length_reset=640*480*4) + cast = structuring.Cast(lasmim.dw, packed_pixels, reverse_to=True) + unpack = structuring.Unpack(pack_factor, pixel_layout) + vtg = VTG() + if simulation: + fifo = sim.SimActor(sim_fifo_gen(), ("dac", Sink, dac_layout)) + else: + fifo = FIFO() - skip = _bpc - _bpc_dac - comb = [ - active.eq(hactive & vactive), - If(active, - self.token("dac").r.eq(self.token("pixels").r[skip:]), - self.token("dac").g.eq(self.token("pixels").g[skip:]), - self.token("dac").b.eq(self.token("pixels").b[skip:]) - ), - - generate_en.eq(self.endpoints["timing"].stb & (~active | self.endpoints["pixels"].stb)), - self.endpoints["pixels"].ack.eq(self.endpoints["dac"].ack & active), - self.endpoints["dac"].stb.eq(generate_en) + g = DataFlowGraph() + g.add_connection(fi, vtg, sink_ep="timing") + g.add_connection(dma, cast) + g.add_connection(cast, unpack) + g.add_connection(unpack, vtg, sink_ep="pixels") + g.add_connection(vtg, fifo) + self.submodules += CompositeActor(g) + + self._enable = CSRStorage() + self.comb += [ + fi.trigger.eq(self._enable.storage), + dma.generator.trigger.eq(self._enable.storage), ] - tp = self.token("timing") - sync = [ - self.endpoints["timing"].ack.eq(0), - If(generate_en & self.endpoints["dac"].ack, - hcounter.eq(hcounter + 1), - - If(hcounter == 0, hactive.eq(1)), - If(hcounter == tp.hres, hactive.eq(0)), - If(hcounter == tp.hsync_start, self.token("dac").hsync.eq(1)), - If(hcounter == tp.hsync_end, self.token("dac").hsync.eq(0)), - If(hcounter == tp.hscan, - hcounter.eq(0), - If(vcounter == tp.vscan, - vcounter.eq(0), - self.endpoints["timing"].ack.eq(1) + self._fi = fi + self._dma = dma + + # Drive pads + if not simulation: + self.comb += [ + pads.hsync_n.eq(fifo.vga_hsync_n), + pads.vsync_n.eq(fifo.vga_vsync_n), + pads.r.eq(fifo.vga_r), + pads.g.eq(fifo.vga_g), + pads.b.eq(fifo.vga_b) + ] + self.comb += pads.psave_n.eq(1) + + def get_csrs(self): + return [self._enable] + self._fi.get_csrs() + self._dma.get_csrs() + +class Blender(PipelinedActor, AutoCSR): + def __init__(self, nimages, latency): + self.sink = Sink([("i"+str(i), pixel_layout) for i in range(nimages)]) + self.source = Source(pixel_layout) + factors = [] + for i in range(nimages): + name = "f"+str(i) + csr = CSRStorage(8, name=name) + setattr(self, name, csr) + factors.append(csr.storage) + PipelinedActor.__init__(self, latency) + + ### + + imgs = [getattr(self.sink.payload, "i"+str(i)) for i in range(nimages)] + outval = Record(pixel_layout) + for e in pixel_layout: + name = e[0] + inpixs = [getattr(img, name) for img in imgs] + outpix = getattr(outval, name) + for component in ["r", "g", "b"]: + incomps = [getattr(pix, component) for pix in inpixs] + outcomp = getattr(outpix, component) + outcomp_full = Signal(19) + self.comb += [ + outcomp_full.eq(sum(incomp*factor for incomp, factor in zip(incomps, factors))), + If(outcomp_full[18], + outcomp.eq(2**10 - 1) # saturate on overflow ).Else( - vcounter.eq(vcounter + 1) + outcomp.eq(outcomp_full[8:18]) ) - ), - - If(vcounter == 0, vactive.eq(1)), - If(vcounter == tp.vres, vactive.eq(0)), - If(vcounter == tp.vsync_start, self.token("dac").vsync.eq(1)), - If(vcounter == tp.vsync_end, self.token("dac").vsync.eq(0)) - ) - ] - - return Fragment(comb, sync) + ] -class FIFO(Actor): - def __init__(self): - super().__init__(("dac", Sink, _dac_layout)) + pipe_stmts = [] + for i in range(latency): + new_outval = Record(pixel_layout) + pipe_stmts.append(new_outval.eq(outval)) + outval = new_outval + self.sync += If(self.pipe_ce, pipe_stmts) + self.comb += self.source.payload.eq(outval) + +class MixFramebuffer(Module, AutoCSR): + def __init__(self, pads, *lasmims, blender_latency=5): + pack_factor = lasmims[0].dw//(2*bpp) + packed_pixels = structuring.pack_layout(pixel_layout, pack_factor) - self.vga_hsync_n = Signal() - self.vga_vsync_n = Signal() - self.vga_r = Signal(_bpc_dac) - self.vga_g = Signal(_bpc_dac) - self.vga_b = Signal(_bpc_dac) - - def get_fragment(self): - data_width = 2+3*_bpc_dac - fifo_full = Signal() - fifo_write_en = Signal() - fifo_data_out = Signal(data_width) - fifo_data_in = Signal(data_width) - asfifo = Instance("asfifo", - Instance.Parameter("data_width", data_width), - Instance.Parameter("address_width", 8), - - Instance.Output("data_out", fifo_data_out), - Instance.Output("empty"), - Instance.Input("read_en", 1), - Instance.ClockPort("clk_read", "vga"), + self._enable = CSRStorage() + self.fi = FrameInitiator() + self.blender = Blender(len(lasmims), blender_latency) + self.comb += self.fi.trigger.eq(self._enable.storage) - Instance.Input("data_in", fifo_data_in), - Instance.Output("full", fifo_full), - Instance.Input("write_en", fifo_write_en), - Instance.ClockPort("clk_write"), - - Instance.Input("rst", 0)) - t = self.token("dac") - return Fragment( - [ - Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.get_io("data_out")), - - self.endpoints["dac"].ack.eq(~fifo_full), - fifo_write_en.eq(self.endpoints["dac"].stb), - fifo_data_in.eq(Cat(~t.hsync, ~t.vsync, t.r, t.g, t.b)), - - self.busy.eq(0) - ], - instances=[asfifo]) + g = DataFlowGraph() + for n, lasmim in enumerate(lasmims): + dma = spi.DMAReadController(dma_lasmi.Reader(lasmim), spi.MODE_EXTERNAL, length_reset=640*480*4) + cast = structuring.Cast(lasmim.dw, packed_pixels, reverse_to=True) + unpack = structuring.Unpack(pack_factor, pixel_layout) -def sim_fifo_gen(): - while True: - t = sim.Token("dac") - yield t - print("H/V:" + str(t.value["hsync"]) + str(t.value["vsync"]) - + " " + str(t.value["r"]) + " " + str(t.value["g"]) + " " + str(t.value["b"])) + g.add_connection(dma, cast) + g.add_connection(cast, unpack) + g.add_connection(unpack, self.blender, sink_subr=["i"+str(n)]) + self.comb += dma.generator.trigger.eq(self._enable.storage) + setattr(self, "dma"+str(n), dma) -class Framebuffer: - def __init__(self, address, asmiport, simulation=False): - asmi_bits = asmiport.hub.aw - alignment_bits = bits_for(asmiport.hub.dw//8) - 1 - length_bits = _hbits + _vbits + 2 - alignment_bits - pack_factor = asmiport.hub.dw//_bpp - packed_pixels = structuring.pack_layout(_pixel_layout, pack_factor) - - fi = _FrameInitiator(asmi_bits, length_bits, alignment_bits) - adrloop = misc.IntSequence(length_bits, asmi_bits) - adrbuffer = AbstractActor(plumbing.Buffer) - dma = dma_asmi.Reader(asmiport) - datbuffer = AbstractActor(plumbing.Buffer) - cast = structuring.Cast(asmiport.hub.dw, packed_pixels) - unpack = structuring.Unpack(pack_factor, _pixel_layout) vtg = VTG() - if simulation: - fifo = sim.SimActor(sim_fifo_gen(), ("dac", Sink, _dac_layout)) - else: - fifo = FIFO() - - g = DataFlowGraph() - g.add_connection(fi, adrloop, source_subr=["length", "base"]) - g.add_connection(adrloop, adrbuffer) - g.add_connection(adrbuffer, dma) - g.add_connection(dma, datbuffer) - g.add_connection(datbuffer, cast) - g.add_connection(cast, unpack) - g.add_connection(unpack, vtg, sink_ep="pixels") - g.add_connection(fi, vtg, sink_ep="timing", source_subr=[ - "hres", "hsync_start", "hsync_end", "hscan", - "vres", "vsync_start", "vsync_end", "vscan"]) + fifo = FIFO() + g.add_connection(self.fi, vtg, sink_ep="timing") + g.add_connection(self.blender, vtg, sink_ep="pixels") g.add_connection(vtg, fifo) - self._comp_actor = CompositeActor(g, debugger=False) + self.submodules += CompositeActor(g) - self.bank = csrgen.Bank(fi.get_registers() + self._comp_actor.get_registers(), - address=address) - - # Pads - self.vga_psave_n = Signal() - if not simulation: - self.vga_hsync_n = fifo.vga_hsync_n - self.vga_vsync_n = fifo.vga_vsync_n - self.vga_sync_n = Signal() - self.vga_blank_n = Signal() - if not simulation: - self.vga_r = fifo.vga_r - self.vga_g = fifo.vga_g - self.vga_b = fifo.vga_b - - def get_fragment(self): - comb = [ - self.vga_sync_n.eq(0), - self.vga_psave_n.eq(1), - self.vga_blank_n.eq(1) + self.comb += [ + pads.hsync_n.eq(fifo.vga_hsync_n), + pads.vsync_n.eq(fifo.vga_vsync_n), + pads.r.eq(fifo.vga_r), + pads.g.eq(fifo.vga_g), + pads.b.eq(fifo.vga_b), + pads.psave_n.eq(1) ] - return self.bank.get_fragment() \ - + self._comp_actor.get_fragment() \ - + Fragment(comb)