X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=nlnet_2019_coriolis2.mdwn;h=a3f298bfb1a50f90338439ed150da862ec4077b1;hb=3fca0b5a420965cc7c5a8370941f0ab3ecb8ba5f;hp=11cefa8cc8d933e653d4802ce25464535c0819e1;hpb=d596f73ea8cb148757ea480cb0163f8567320f76;p=libreriscv.git
diff --git a/nlnet_2019_coriolis2.mdwn b/nlnet_2019_coriolis2.mdwn
index 11cefa8cc..a3f298bfb 100644
--- a/nlnet_2019_coriolis2.mdwn
+++ b/nlnet_2019_coriolis2.mdwn
@@ -1,12 +1,19 @@
-# NL.net proposal
+# NLnet.net LIP6.fr Coriolis2 proposal
+
+* [[questions]]
+* approved 20dec2019
+* MOU done
+* 2019-10-029
+* NLNet Project Page
+* Top-level bugreport
## Project name
-The Libre-RISCV SoC, Coriolis2 ASIC Layout Collaboration
+Libre-SoC, Coriolis2 ASIC Layout Collaboration
## Website / wiki
-
+
Please be short and to the point in your answers; focus primarily on
the what and how, not so much on the why. Add longer descriptions as
@@ -29,10 +36,10 @@ It is necessary, therefore, to use libre-licensed VLSI Layout tools
rather than pay for proprietary software that, apart from being incredibly
expensive, could potentially compromise the integrity of the project.
-We therefore intend to collaborate with engineers from the Laboratoire
-d'Informatique de Paris 6, to use and improve their VLSI Layout tool,
-Coriolis2, in conjunction with Chips4Makers, to create the layout that
-Chips4Makers will then put into a 180nm 300mhz test chip.
+We therefore intend to collaborate with engineers from LIP6, to use
+and improve their VLSI Layout tool, Coriolis2, in conjunction with
+Chips4Makers, to create the layout that Chips4Makers will then put into
+a 180nm 300mhz test chip.
# Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
@@ -42,8 +49,7 @@ Luke Leighton is an ethical technology specialist who has a consistent
lead developer on the Libre RISC-V SoC.
Jean-Paul Chaput is the lead engineer on the Alliance and Coriolis2
-tools for VLSI backend layout, from the Laboratoire d'Informatique de
-Paris 6.
+tools for VLSI backend layout, from LIP6.
# Requested Amount
@@ -86,7 +92,7 @@ So therefore, the requested budget will be used for:
* Essential augmentations to nmigen to make it ASIC-layout-capable
All of these will be and are entirely libre-licensed software: there will
-be no proprietary software tools utilised in this process. Note that
+be no proprietary software tools utilised in this process.
# Does the project have other funding sources, both past and present?