X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=nlnet_2019_coriolis2.mdwn;h=a3f298bfb1a50f90338439ed150da862ec4077b1;hb=ccfc957b55d0163099cb66301bcfe30ca1b8e6b4;hp=c6b5e69f0f341c110733fb659a1ddbb3e429f62f;hpb=92d479dbdce5d4a6bbd7875d31f1c11e736122db;p=libreriscv.git

diff --git a/nlnet_2019_coriolis2.mdwn b/nlnet_2019_coriolis2.mdwn
index c6b5e69f0..a3f298bfb 100644
--- a/nlnet_2019_coriolis2.mdwn
+++ b/nlnet_2019_coriolis2.mdwn
@@ -1,12 +1,19 @@
-# NL.net proposal
+# NLnet.net LIP6.fr Coriolis2 proposal
+
+* [[questions]]
+* approved 20dec2019
+* MOU done
+* 2019-10-029
+* NLNet Project Page <https://nlnet.nl/project/Coriolis2/>
+* Top-level bugreport <http://bugs.libre-riscv.org/show_bug.cgi?id=138>
 
 ## Project name
 
-The Libre-RISCV SoC, Coriolis2 ASIC Layout Collaboration
+Libre-SoC, Coriolis2 ASIC Layout Collaboration
 
 ## Website / wiki 
 
-<https://libre-riscv.org/nlnet_2019_coriolis2>
+<https://libre-soc.org/nlnet_2019_coriolis2>
 
 Please be short and to the point in your answers; focus primarily on
 the what and how, not so much on the why. Add longer descriptions as