X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=nlnet_2019_gcc.mdwn;h=8d1d3ba00dd337796c1313ad0a013a83f7856cc7;hb=836c45ec89a62cca9433f94a4f3603d52aad0c80;hp=73134991d27cda1a61996c58bbc40e7f5e9f75b8;hpb=5ef2c9cc6c41f428aabe3670e394fa444b275e40;p=libreriscv.git

diff --git a/nlnet_2019_gcc.mdwn b/nlnet_2019_gcc.mdwn
index 73134991d..8d1d3ba00 100644
--- a/nlnet_2019_gcc.mdwn
+++ b/nlnet_2019_gcc.mdwn
@@ -78,6 +78,22 @@ Whatever other compiler projects exist, they are just not compatible at the asse
 
 This is just a standard part of processor innovation.  We will also have to do the same thing for LLVM at some point.
 
+# What are significant technical challenges you expect to solve during the project, if any?
+
+Compiler development is known, traditionally, to be extremely technically
+challenging.  There are not many people in the world who work on it.
+Vectorisation support is even more challenging, and is a fast-moving
+research topic.  Fortunately there is convergent research in this area,
+however with this processor's Vectorisation being literally unique,
+and also in active development (requiring an iterative process), this is
+going to be a huge challenge.  Luckily, there is low-hanging fruit that
+will allow significant performance increases for relatively little compiler
+effort.
+
+Keeping the work upstream is made difficult because there is not yet any
+active silicon.  Part of the tasks will therefore be to ensure that the
+code is kept up-to-date until such time as active silicon is available.
+
 ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
 
 As mentioned in the 2018 submission, the Libre RISC-V