X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=nlnet_2021_3mdeb_cavatools.mdwn;h=d9f4ea155e5ddbe5bcd3540c6b6c522d6fb5beb7;hb=367bd556802220231196bb05c0b8ff76a45338ed;hp=61cefa413f20ca1d555c3b5aa62f9ce624b7cca6;hpb=6ece8e24352694a75a6d404134dfb89d526a9e86;p=libreriscv.git diff --git a/nlnet_2021_3mdeb_cavatools.mdwn b/nlnet_2021_3mdeb_cavatools.mdwn index 61cefa413..d9f4ea155 100644 --- a/nlnet_2021_3mdeb_cavatools.mdwn +++ b/nlnet_2021_3mdeb_cavatools.mdwn @@ -1,3 +1,9 @@ +# NLnet User-operated Grant Request for 3mdeb Power ISA Simulator + +* 2021-08-071 +* [[nlnet_2021_3mdeb_cavatools/discussion]] +* + ## Project name Libre-SOC 3mdeb Cavatools: Power ISA Simulator @@ -30,7 +36,7 @@ is expected. # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions? 3mdeb is currently helping Libre-SOC with the (horribly slow, -easy-to-read) Libre-SOC Power ISA Simulator which is 20,000 times +easy-to-read, easy-to-use) Libre-SOC Power ISA Simulator which is 20,000 times slower than cavatools. 3mdeb is also helping with ISA level unit tests in Libre-SOC's code base that will be used to cross-validate a huge range of Power ISA simulators and actual silicon implementations. @@ -53,22 +59,52 @@ EUR $50,000. initramfs in-memory with basic serial console access * To demonstrate running first a single core linux kernel and later a SMP one, with busybox -* To use the exact same Spec c compiler to create +* To use the exact same Specification c compiler to create an "illegal instruction trap" emulator, integrated - into the linux kernel for emulating SIMD instructions. + into the linux kernel, for emulating Power ISA SIMD instructions + (extending the existing trap-and-emulate code already present + in ppc64 linux kernel source code) # Does the project have other funding sources, both past and present? Although there is NLnet funding for the Libre-SOC Simulator (written in python) and associayed unit tests, cavatools, which is written in c by Peter Hsu, does not have funding for the Power ISA -aditions. +aditions. cavatools itself is a very new project. # Compare your own project with existing or historical efforts. +Although there are quite a few Power ISA simulators, none of them +are up-to-date or are suited to high performance, like cavatools. +cavatools is multi-process and extremely fast, using relatively little +memory, where power-gem5, which has a different focus and has huge flexibility +and usefulness for research, uses vast amounts +of memory and is much slower. cavatools also has hardware-level cycle-accurate emulation which is extremely useful and important for analysing experimental +instructions, which is a feature that no other Power ISA Simulator has. +DolphinPC and pearpc are over 15 years old and were targetted at 32 bit +emulation of much older Power ISA processors. Libre-SOC's python-based +simulator only achieves aroubd 2,000 instructions per second on +high performance hardware whereas +cavatools achieves 200,000 instructions per second per processor +on modest hardware. +IBM's own Power ISA simulator is proprietary and, because it contains +confidential experimentation internal to IBM, may not be made public. + ## What are significant technical challenges you expect to solve during the project, if any? +This is at its heart a compiler project, which can be a challenging +area. However the language being implemented is quite small and limited, +so the project is relatively straightforward. ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes? +The project will be developed entirely publicly and transparently, +using Libre-SOC Project Resources which are already set up for trustable +auditability and transparency. The mailing lists therefore are always +publicly available. + +Online conferences and talks will be given as progress +is made, as well as working with Libre-SOC to send out development +reports and progress. + # Extra info to be submitted