X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=nlnet_2022_opf_isa_wg.mdwn;h=ce5f72324835953aa23d068a8ec75ad9009aefc4;hb=db45ed892b252d09bfdfe186a463a59d1ea8b679;hp=dc7d6e64715e285632d31c7ada2e55d7900a5b54;hpb=4c3ddc1b0b0c21e55c958852ff60277a7155bf78;p=libreriscv.git

diff --git a/nlnet_2022_opf_isa_wg.mdwn b/nlnet_2022_opf_isa_wg.mdwn
index dc7d6e647..ce5f72324 100644
--- a/nlnet_2022_opf_isa_wg.mdwn
+++ b/nlnet_2022_opf_isa_wg.mdwn
@@ -1,7 +1,8 @@
 # NL.net proposal
 
-* 2022-08-051
-* [[discussion]]
+* 2022-08-051, approved 24 Oct 2022
+* [[nlnet_2022_opf_isa_wg/discussion]]
+* <https://bugs.libre-soc.org/show_bug.cgi?id=952>
 
 ## Project name
 
@@ -11,6 +12,22 @@ Libre-SOC OpenPOWER ISA RFCs
 
 <https://libre-soc.org/nlnet_2022_opf_isa_wg>
 
+# Summary
+
+In earlier NLnet Grants, thanks to EU funding, we developed Draft
+SVP64 (a Vector Extension for the Power ISA), around a hundred
+new Draft instructions that dramatically improves the Supercomputing-class
+Power ISA, a Simulator, thousands
+of unit tests and over 350 pages of documentation.  What we could
+not do however was submit a Specification to the OpenPOWER ISA
+Working Group because the ISA WG was in the process of being
+ratified.  That has now been done, and we need to begin the
+formal process of writing up "Requests For Change" and submitting
+them. The end result will be an extremely powerful Vector ISA suitable
+for use in Digitally-Sovereign end-user products.
+
+# Submission to NLnet
+
 Please be short and to the point in your answers; focus primarily on
 the what and how, not so much on the why. Add longer descriptions as
 attachments (see below). If English isn't your first language, don't