X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=nlnet_2023_simplev_riscv.mdwn;h=0ef20a1f0b0b6f00a444bd84a22d49727b50e7bf;hb=62918721dc0acd36c5913e02aaf657dd1150f4b2;hp=36ecc7d4b8e061fb08ebe6b5bc6627fcaac86e9a;hpb=687bf18d05231f055235df2afec96ba1013697e6;p=libreriscv.git diff --git a/nlnet_2023_simplev_riscv.mdwn b/nlnet_2023_simplev_riscv.mdwn index 36ecc7d4b..0ef20a1f0 100644 --- a/nlnet_2023_simplev_riscv.mdwn +++ b/nlnet_2023_simplev_riscv.mdwn @@ -1,7 +1,7 @@ # NLnet Simple-V ISA Expansion Project Grant -* Code: 2023-12-XXX -* Submitted: XX Dec 2023 +* Code: 2023-12-059 +* Submitted: 24 Nov 2023 * Toplevel bugreport: This project is applying for funding through the [NGI Zero Core Fund](https://nlnet.nl/core), a fund established by [NLnet](https://nlnet.nl) with financial support from the European Commission's [Next Generation Internet](https://ngi.eu) programme under grant agreement No 101092990. @@ -11,11 +11,11 @@ This project is applying for funding through the [NGI Zero Core Fund](https://nl ## Project name -SVP64 ISA Expansion Project +Simple-V ISA Expansion Project ## Website / wiki - + Please be short and to the point in your answers; focus primarily on the what and how, not so much on the why. Add longer descriptions as @@ -35,7 +35,7 @@ RISC-V is the largest open-source global community for microprocessor architectu # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions? -A sequence of projects has enabled early development of vectorisation techniques in the RISC-V domain, and higher performance demonstration with OpenPOWER ISA. This project takes the learnings from previous projects to create a powerful RISC-V based vector ISA capable of the performance of the Power ISA. A full project list is maintained at: +A sequence of projects has enabled early development of vectorisation techniques in the RISC-V domain, and higher performance demonstration with OpenPOWER ISA. This project takes the learnings and work from previous projects to update RISC-V to a powerful vector ISA capable of the performance of the Power ISA. A full project list is maintained at: they include recently: * - improving SVP64 @@ -75,6 +75,7 @@ Key phases of this project are: the RISC-V/Simple-V environment * Research and assessment of ARM7 and i486 (both on opencores.org) as well as ARC as to their feasibility for applying Simple-V Prefixing in future development projects +* Development and publication of paper in Academic Journals and presentation # Does the project have other funding sources, both past and present? @@ -83,19 +84,27 @@ for this development programme over the past five years, and for the project in # Compare your own project with existing or historical efforts. +Other modern ISAs claiming to be Vectors are in fact Packed or Predicated SIMD. +True Cray-style Vector ISAs do not have Vertical-First or Data-Dependent +Fail-First because these are entirely novel Computer Science concepts +(developnet of which entirely funded by NLnet, with gratitude). +Bottom line there are zero comparable projects but the project has learned +significantly from past ISAs dating back as far as the early 1960s. + ## What are significant technical challenges you expect to solve during the project, if any? -The key technical challenge in this project is the creation of special Simple-V -instructions that enable efficiency and performance from RISC-V that would normally only be obtained from high performance architectures like POWER. The newly developed instructions will be comprehensively tested and verified, both theoretically and practically in a simulator that leads the way to its use in the widespread developer community. +The key technical challenge in this project is to rework the special Simple-V +instructions (from the early iteration of four years ago) that enable efficiency and performance from RISC-V that would normally only be obtained from high performance architectures like POWER. The newly developed instructions will be comprehensively tested and verified, both theoretically and practically in a simulator that leads the way to its use in the widespread developer community. Based on the previous work of Vectorising RISC-V and POWER using Simple-V already, this project is well within the scope of the experienced teams at LibreSOC and RED Semiconductor, but is extremely detailed and comprehensive, requiring meticulous attention to detail and a very high standard of Project Management. This is a sustained standard and practices developed already over a five year period that will continue to be rigorously applied. ## Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes? -The Libre-SoC has a full set of resources for Libre Project Management and development: mailing list, bugtracker, git repository, wiki and also will be doing linkedin posts in other outreach - all listed here: https://libre-soc.org/ - - +Libre-SoC has a full set of resources for Libre Project Management and development: mailing list, bugtracker, git repository, wiki and also will be doing linkedin posts and other outreach as well as Academic-quality papers - all listed here: # Extra info to be submitted +This grant is associated with the binutils grant + + # Questions Received date: TODO