X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=nmigen_soc%2Fwishbone%2Fbus.py;h=ba5bc86efab1ff37d0e0989cfb0237f35ec07924;hb=f1a8aa5206afeee7ced490a719bd671c5c247cf4;hp=039413dff018847be07524e1a02e6d559006602a;hpb=46e37604497be0c26aa807b54d74c50e156b043a;p=nmigen-soc.git diff --git a/nmigen_soc/wishbone/bus.py b/nmigen_soc/wishbone/bus.py index 039413d..ba5bc86 100644 --- a/nmigen_soc/wishbone/bus.py +++ b/nmigen_soc/wishbone/bus.py @@ -30,13 +30,15 @@ class BurstTypeExt(Enum): class Interface(Record): """Wishbone interface. - See the `Wishbone specification `_ for description - of the Wishbone signals. The ``RST_I`` and ``CLK_I`` signals are provided as a part of - the clock domain that drives the interface. + See the `Wishbone specification + `_ for description of the + Wishbone signals. The ``RST_I`` and ``CLK_I`` signals are provided + as a part of the clock domain that drives the interface. - Note that the data width of the underlying memory map of the interface is equal to port - granularity, not port size. If port granularity is less than port size, then the address width - of the underlying memory map is extended to reflect that. + Note that the data width of the underlying memory map of the interface + is equal to port granularity, not port size. If port granularity is + less than port size, then the address width of the underlying memory + map is extended to reflect that. Parameters ---------- @@ -46,9 +48,9 @@ class Interface(Record): Width of the data signals ("port size" in Wishbone terminology). One of 8, 16, 32, 64. granularity : int or None - Granularity of select signals ("port granularity" in Wishbone terminology). - One of 8, 16, 32, 64. Optional and defaults to None, meaning it is equal - to the address width. + Granularity of select signals ("port granularity" in Wishbone + terminology). One of 8, 16, 32, 64. Optional and defaults to + None, meaning it is equal to the address width. features : iter(str) Selects the optional signals that will be a part of this interface. alignment : int @@ -58,37 +60,52 @@ class Interface(Record): Attributes ---------- - The correspondence between the nMigen-SoC signals and the Wishbone signals changes depending - on whether the interface acts as an initiator or a target. + The correspondence between the nMigen-SoC signals and the Wishbone + signals changes depending on whether the interface acts as an + initiator or a target. adr : Signal(addr_width) - Corresponds to Wishbone signal ``ADR_O`` (initiator) or ``ADR_I`` (target). + Corresponds to Wishbone signal ``ADR_O`` (initiator) or ``ADR_I`` + (target). dat_w : Signal(data_width) - Corresponds to Wishbone signal ``DAT_O`` (initiator) or ``DAT_I`` (target). + Corresponds to Wishbone signal ``DAT_O`` (initiator) or ``DAT_I`` + (target). dat_r : Signal(data_width) - Corresponds to Wishbone signal ``DAT_I`` (initiator) or ``DAT_O`` (target). + Corresponds to Wishbone signal ``DAT_I`` (initiator) or ``DAT_O`` + (target). sel : Signal(data_width // granularity) - Corresponds to Wishbone signal ``SEL_O`` (initiator) or ``SEL_I`` (target). + Corresponds to Wishbone signal ``SEL_O`` (initiator) or ``SEL_I`` + (target). cyc : Signal() - Corresponds to Wishbone signal ``CYC_O`` (initiator) or ``CYC_I`` (target). + Corresponds to Wishbone signal ``CYC_O`` (initiator) or ``CYC_I`` + (target). stb : Signal() - Corresponds to Wishbone signal ``STB_O`` (initiator) or ``STB_I`` (target). + Corresponds to Wishbone signal ``STB_O`` (initiator) or ``STB_I`` + (target). we : Signal() - Corresponds to Wishbone signal ``WE_O`` (initiator) or ``WE_I`` (target). + Corresponds to Wishbone signal ``WE_O`` (initiator) or ``WE_I`` + (target). ack : Signal() - Corresponds to Wishbone signal ``ACK_I`` (initiator) or ``ACK_O`` (target). + Corresponds to Wishbone signal ``ACK_I`` (initiator) or ``ACK_O`` + (target). err : Signal() - Optional. Corresponds to Wishbone signal ``ERR_I`` (initiator) or ``ERR_O`` (target). + Optional. Corresponds to Wishbone signal ``ERR_I`` (initiator) + or ``ERR_O`` (target). rty : Signal() - Optional. Corresponds to Wishbone signal ``RTY_I`` (initiator) or ``RTY_O`` (target). + Optional. Corresponds to Wishbone signal ``RTY_I`` (initiator) + or ``RTY_O`` (target). stall : Signal() - Optional. Corresponds to Wishbone signal ``STALL_I`` (initiator) or ``STALL_O`` (target). + Optional. Corresponds to Wishbone signal ``STALL_I`` (initiator) + or ``STALL_O`` (target). lock : Signal() - Optional. Corresponds to Wishbone signal ``LOCK_O`` (initiator) or ``LOCK_I`` (target). + Optional. Corresponds to Wishbone signal ``LOCK_O`` (initiator) + or ``LOCK_I`` (target). cti : Signal() - Optional. Corresponds to Wishbone signal ``CTI_O`` (initiator) or ``CTI_I`` (target). + Optional. Corresponds to Wishbone signal ``CTI_O`` (initiator) + or ``CTI_I`` (target). bte : Signal() - Optional. Corresponds to Wishbone signal ``BTE_O`` (initiator) or ``BTE_I`` (target). + Optional. Corresponds to Wishbone signal ``BTE_O`` (initiator) + or ``BTE_I`` (target). """ def __init__(self, *, addr_width, data_width, granularity=None, features=frozenset(), alignment=0, name=None): @@ -216,12 +233,14 @@ class Decoder(Elaboratable): def add(self, sub_bus, *, addr=None, sparse=False): """Add a window to a subordinate bus. - The decoder can perform either sparse or dense address translation. If dense address - translation is used (the default), the subordinate bus must have the same data width as - the decoder; the window will be contiguous. If sparse address translation is used, - the subordinate bus may have data width less than the data width of the decoder; - the window may be discontiguous. In either case, the granularity of the subordinate bus - must be equal to or less than the granularity of the decoder. + The decoder can perform either sparse or dense address + translation. If dense address translation is used (the default), + the subordinate bus must have the same data width as the decoder; + the window will be contiguous. If sparse address translation is + used, the subordinate bus may have data width less than the data + width of the decoder; the window may be discontiguous. In either + case, the granularity of the subordinate bus must be equal to + or less than the granularity of the decoder. See :meth:`MemoryMap.add_resource` for details. """ @@ -319,8 +338,8 @@ class Arbiter(Elaboratable): features : iter(str) Optional signal set for the shared bus. See :class:`Interface`. scheduler : str - Method for bus arbitration. Optional and defaults to "rr" (Round Robin, see - :class:`scheduler.RoundRobin`). + Method for bus arbitration. Optional and defaults to "rr" + (Round Robin, see :class:`scheduler.RoundRobin`). Attributes ---------- @@ -340,9 +359,9 @@ class Arbiter(Elaboratable): def add(self, itor_bus): """Add an initiator bus to the arbiter. - The initiator bus must have the same address width and data width as the arbiter. The - granularity of the initiator bus must be greater than or equal to the granularity of - the arbiter. + The initiator bus must have the same address width and data + width as the arbiter. The granularity of the initiator bus must + be greater than or equal to the granularity of the arbiter. """ if not isinstance(itor_bus, Interface): raise TypeError("Initiator bus must be an instance of wishbone.Interface, not {!r}" @@ -452,16 +471,17 @@ class InterconnectShared(Elaboratable): If the item is a :class:`Record`, its fields must be named using the convention of :class:`Interface`. targets : list of (:class:`Interface` OR tuple of (:class:`Interface`, int)) - List of SLAVEs on the decoder whose accesses are to be targeted by the shared bus. - If the item is a tuple of (intf, addr), the :class:`Interface`-type intf is added - at the (address width + granularity bits)-wide address of the int-type addr. + List of SLAVEs on the decoder whose accesses are to be targeted + by the shared bus. If the item is a tuple of (intf, addr), the + :class:`Interface`-type intf is added at the (address width + + granularity bits)-wide address of the int-type addr. granularity : int or None Granularity of the shared bus. Optional. See :class:`Interface`. features : iter(str) Optional signal set for the shared bus. See :class:`Interface`. scheduler : str - Method for bus arbitration for the arbiter. Optional and defaults to "rr" (Round Robin, see - :class:`scheduler.RoundRobin`). + Method for bus arbitration for the arbiter. Optional and defaults + to "rr" (Round Robin, see :class:`scheduler.RoundRobin`). alignment : int Window alignment for the decoder. Optional. See :class:`Interface`.