X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=70b95f3caca61f08cbe0b4404437748b06f89fe8;hb=9819647a63bfca45a879650ac23fe80f51b89edb;hp=4f5e200e38d94264447468fd8a97269d8dadf124;hpb=66e6f0b760c2480e4ebdac8169adcee1fc31f689;p=binutils-gdb.git

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4f5e200e38d..70b95f3caca 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,81 @@
+2018-11-06  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
+	* i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
+	cases up one level in the hierarchy.
+
+2018-11-06  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
+	MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
+	(MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
+	into MOD_VEX_0F93_P_3_LEN_0.
+	(vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
+	operand cases up one level in the hierarchy.
+
+2018-11-06  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
+	VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
+	EVEX_W_0F3A22_P_2): Delete.
+	(vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
+	entries up one level in the hierarchy.
+	(OP_E_memory): Handle dq_mode when determining Disp8 shift
+	value.
+	* i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
+	entries up one level in the hierarchy.
+	* i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
+	VexWIG for AVX flavors.
+	* i386-tbl.h: Re-generate.
+
+2018-11-06  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
+	vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
+	vcvtusi2ss, kmovd): Drop VexW=1.
+	* i386-tbl.h: Re-generate.
+
+2018-11-06  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
+	EVex512, EVexLIG, EVexDYN): New.
+	(ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
+	insns): Use Vex128 instead of Vex=3 (aka VexLIG).
+	(vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
+	of EVex=4 (aka EVexLIG).
+	* i386-tbl.h: Re-generate.
+
+2018-11-06  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
+	(vpmaxub): Re-order attributes on AVX512BW flavor.
+	* i386-tbl.h: Re-generate.
+
+2018-11-06  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
+	vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
+	Vex=1 on AVX / AVX2 flavors.
+	(vpmaxub): Re-order attributes on AVX512BW flavor.
+	* i386-tbl.h: Re-generate.
+
+2018-11-06  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl (VexW0, VexW1): New.
+	(vphadd*, vphsub*): Use VexW0 on XOP variants.
+	* i386-tbl.h: Re-generate.
+
+2018-10-22  John Darrington  <john@darrington.wattle.id.au>
+
+	* s12z-dis.c (decode_possible_symbol): Add fallback case.
+	(rel_15_7): Likewise.
+
+2018-10-19  Tamar Christina  <tamar.christina@arm.com>
+
+	* arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
+	(UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
+	(print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
+
 2018-10-16  Matthew Malcomson  <matthew.malcomson@arm.com>
 
 	* aarch64-opc.c (struct operand_qualifier_data): Change qualifier data