X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=opcodes%2FChangeLog;h=aa78ea96d5aec591ab54cd966f37f21a5b833596;hb=0067be51e9436c5bbd961a4f54c10dbd50c491ea;hp=d0f28ced24dbfda00e23ca5ac880700b68574067;hpb=3c705960ca0e12bb5d3a12d14ca6703006102d98;p=binutils-gdb.git

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d0f28ced24d..aa78ea96d5a 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,98 @@
+2019-05-11  Alan Modra  <amodra@gmail.com>
+
+	* ppc-dis.c (print_insn_powerpc) Don't skip optional operands
+	when -Mraw is in effect.
+
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+	* aarch64-dis-2.c: Regenerate.
+	* aarch64-tbl.h (OP_SVE_BBU): New variant set.
+	(OP_SVE_BBB): New variant set.
+	(OP_SVE_DDDD): New variant set.
+	(OP_SVE_HHH): New variant set.
+	(OP_SVE_HHHU): New variant set.
+	(OP_SVE_SSS): New variant set.
+	(OP_SVE_SSSU): New variant set.
+	(OP_SVE_SHH): New variant set.
+	(OP_SVE_SBBU): New variant set.
+	(OP_SVE_DSS): New variant set.
+	(OP_SVE_DHHU): New variant set.
+	(OP_SVE_VMV_HSD_BHS): New variant set.
+	(OP_SVE_VVU_HSD_BHS): New variant set.
+	(OP_SVE_VVVU_SD_BH): New variant set.
+	(OP_SVE_VVVU_BHSD): New variant set.
+	(OP_SVE_VVV_QHD_DBS): New variant set.
+	(OP_SVE_VVV_HSD_BHS): New variant set.
+	(OP_SVE_VVV_HSD_BHS2): New variant set.
+	(OP_SVE_VVV_BHS_HSD): New variant set.
+	(OP_SVE_VV_BHS_HSD): New variant set.
+	(OP_SVE_VVV_SD): New variant set.
+	(OP_SVE_VVU_BHS_HSD): New variant set.
+	(OP_SVE_VZVV_SD): New variant set.
+	(OP_SVE_VZVV_BH): New variant set.
+	(OP_SVE_VZV_SD): New variant set.
+	(aarch64_opcode_table): Add sve2 instructions.
+
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+	* aarch64-asm-2.c: Regenerated.
+	* aarch64-dis-2.c: Regenerated.
+	* aarch64-opc-2.c: Regenerated.
+	* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
+	for SVE_SHLIMM_UNPRED_22.
+	(aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
+	* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
+	operand.
+
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
+	sve_size_tsz_bhs iclass encode.
+	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
+	sve_size_tsz_bhs iclass decode.
+
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+	* aarch64-asm-2.c: Regenerated.
+	* aarch64-dis-2.c: Regenerated.
+	* aarch64-opc-2.c: Regenerated.
+	* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
+	for SVE_Zm4_11_INDEX.
+	(aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
+	(fields): Handle SVE_i2h field.
+	* aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
+	* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
+
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
+	sve_shift_tsz_bhsd iclass encode.
+	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
+	sve_shift_tsz_bhsd iclass decode.
+
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+	* aarch64-asm-2.c: Regenerated.
+	* aarch64-dis-2.c: Regenerated.
+	* aarch64-opc-2.c: Regenerated.
+	* aarch64-asm.c (aarch64_ins_sve_shrimm):
+	(aarch64_encode_variant_using_iclass): Handle
+	sve_shift_tsz_hsd iclass encode.
+	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
+	sve_shift_tsz_hsd iclass decode.
+	* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
+	for SVE_SHRIMM_UNPRED_22.
+	(aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
+	* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
+	operand.
+
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
+	sve_size_013 iclass encode.
+	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
+	sve_size_013 iclass decode.
+
 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 
 	* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle