X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=openpower%2Fisa%2Fpifixedstore.mdwn;h=8a45cd96858ca026ec0957baa7f2b50ec6c111c9;hb=8da557b61c8bf245998e165476555568644d960a;hp=627fb24a21ccbc479814e3f9e11996e5ae835189;hpb=32485a09687df34f094171c27e23835b185ec7e9;p=openpower-isa.git

diff --git a/openpower/isa/pifixedstore.mdwn b/openpower/isa/pifixedstore.mdwn
index 627fb24a..8a45cd96 100644
--- a/openpower/isa/pifixedstore.mdwn
+++ b/openpower/isa/pifixedstore.mdwn
@@ -72,9 +72,9 @@ Pseudo-code:
 
 Description:
 
-Let the effective address (EA) be the sum (RA|0)+ D.
-(RS)[48:63] are stored into the halfword in storage
-addressed by EA.
+    Let the effective address (EA) be the sum (RA|0)+ D.
+    (RS)[48:63] are stored into the halfword in storage
+    addressed by EA.
 
 Special Registers Altered:
 
@@ -93,6 +93,16 @@ Pseudo-code:
     MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+    (RS)[56:63] are stored into the byte in storage addressed
+    by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid
+
 Special Registers Altered:
 
     None
@@ -110,6 +120,16 @@ Pseudo-code:
     MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ D.
+    (RS)[32:63] are stored into the word in storage addressed
+    by EA.
+
+    EA is placed into register RA.
+
+    If RA=0, the instruction form is invalid.
+
 Special Registers Altered:
 
     None