X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=openpower%2Fsv%2Fcomparison_table.mdwn;h=3925e82a90d5c634f683d61ea2b8fdf3a62fbf92;hb=cab89c7220dd80c9810074cae995227d3f24c0ba;hp=90041cb115a6f3d1e66dbebf03788c12fc848353;hpb=f04457988e00017b4ba121bc86a2fbe7bdd37a25;p=libreriscv.git
diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn
index 90041cb11..3925e82a9 100644
--- a/openpower/sv/comparison_table.mdwn
+++ b/openpower/sv/comparison_table.mdwn
@@ -1,5 +1,49 @@
-# ISA Comparison Table
+**ISA Comparison Table**
-| Name | Num of
opcodes | Scalable | Predicate
Masks |
-|------|----------------------|----------|------------------------|
-| SVP64| 5 (plus prefixing) | yes | yes |
+|ISA
name |Num
opcodes|Num
intrinsics|Taxonomy /
Class|setvl
scalable|Predicate
Masks|Twin
Predication|Explicit
Vector regs|128-bit
ops|Bigint |LDST
Fault-First|Data-dependent
Fail-first|Predicate-
Result|Matrix HW
support|
+|--------------|---------------|------------------|---------------------|-------------------|--------------------|---------------------|-------------------------|----------------|--------|---------------------|------------------------------|---------------------|---------------------|
+|Draft SVP64 |5 (1) |see (25) |Scalable (2) |yes |yes |yes (3) |no (4) |see (5) |yes (6) |yes (7) |yes (8) |yes (9) |yes (10) |
+|VSX |700+ |700+? (26) |Packed SIMD |no |no |no |yes (11) |yes |no |no |no |no |yes (12) |
+|NEON |~250 (13) |7088 (27) |Packed SIMD |no |no |no |yes |yes |no |no |no |no |no |
+|SVE2 |~1000 (14) |6040 (28) |Predicated SIMD(15) |no (15) |yes |no |yes |yes |no |yes (7) |no |no |no |
+|AVX512 (16) |~1000s (17) |7256 (29) |Predicated SIMD |no |yes |no |yes |yes |no |no |no |no |no |
+|RVV (18) |~190 (19) |~25000 (30) |Scalable (20) |yes |yes |no |yes |yes (21) |no |yes |no |no |no |
+|Aurora SX(22) |~200 (23) |unknown (31) |Scalable (24) |yes |yes |no |yes |no |no |no |no |no |no |
+
+* (1): plus EXT001 24-bit prefixing using 25% of EXT001 space. See [[sv/svp64]]
+* (2): A 2-Dimensional Scalable Vector ISA **specifically designed for the Power ISA** with both Horizontal-First and Vertical-First Modes. See [[sv/vector_isa_comparison]]
+* (3): on specific operations. See [[opcode_regs_deduped]] for full list. Key: 2P - Twin Predication, 1P - Single-Predicate
+* (4): SVP64 provides a Vector concept on top of the **Scalar** GPR, FPR and CR Fields, extended to 128 entries.
+* (5): SVP64 Vectorises Scalar ops. It is up to the **implementor** to choose (**optionally**) whether to apply SVP64 to e.g. VSX Quad-Precision (128-bit) instructions, to create 128-bit Vector ops.
+* (6): big-integer add is just `sv.adde`. For optimal performance Bigint Mul and divide first require addition of two scalar operations (which are then naturally Vectorised by SVP64). See [[sv/biginteger/analysis]]
+* (7): See [[sv/svp64/appendix]] and [ARM SVE Fault-First](https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf)
+* (8): Based on LD/ST Fail-first, extended to data. See [[sv/svp64/appendix]]
+* (9): Turns standard ops into a type of "cmp". See [[sv/svp64/appendix]]
+* (10): Any non-power-of-two Matrix up to 127 FMACs. Also DCT (Lee) and FFT Full (RADIX2) Triple-loops supported. See [[sv/remap]]
+* (11): VSX's Vector Registers are mis-named: they are 100% PackedSIMD. AVX-512 is not a Vector ISA either. See [Flynn's Taxonomy](https://en.wikipedia.org/wiki/Flynn%27s_taxonomy)
+* (12): Power ISA v3.1 contains "Matrix Multiply Assist" (MMA) which due to PackedSIMD is restricted to RADIX2 and requires inline assembler loop-unrolling for non-power-of-two Matrix dimensions
+* (13): difficult to ascertain, see [NEON/VFP](https://developer.arm.com/documentation/den0018/a/NEON-and-VFP-Instruction-Summary/List-of-all-NEON-and-VFP-instructions).
+ Critically depends on ARM Scalar instructions
+* (14): difficult to exactly ascertain, see ARM Architecture Reference Manual Supplement, DDI 0584. Critically depends on ARM Scalar instructions.
+* (15): ARM states that the Scalability is a [Silicon-partner choice](https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/102340_0001_00_en_introduction-to-sve2.pdf?revision=aae96dd2-5334-4ad3-9a47-393086a20fea).
+ Scalability in the ISA is **not available to the programmer**: there is no `setvl` instruction in SVE2, which is already causing assembler programmer difficulties. Effectively this makes SVE2 Predicated SIMD where the SIMD width is chosen by the "Silicon partner".
+ **Assessing binary non-portability, acknowledged PRIVATELY by ARM Engineers, requires in-depth knowledge of SVE2. This has NOT yet reached public awareness due to total world-wide lack of SVE2 Hardware**
+* (16): [AVX512 Wikipedia](https://en.wikipedia.org/wiki/AVX-512), [Lifecycle of an instruction set](https://media.handmade-seattle.com/tom-forsyth/) including full slides
+* (17): difficult to exactly ascertain, contains subsets. Critically depends on ISA support from earlier x86 ISA subsets (several more thousand instructions). See [SIMD ISA listing](https://www.officedaytime.com/simd512e/)
+* (18): [RVV Spec](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc)
+* (19): RISC-V Vectors are not stand-alone, i.e. like SVE2 and AVX-512 are critically dependent on the Scalar ISA (an additional ~96 instructions for the Scalar RV64GC set (RV64GC is equivalent to the Linux Compliancy Level)
+* (20): Like the original Cray RVV is a truly scalable Vector ISA (Cray setvl instruction). However, like SVE2, the Maximum Vector length is a Silicon-partner choice, which creates similar limitations that SVP64 does not have.
+ The RISC-V Founders strongly discourage efforts by programmers to find out the Silicon's Maximum Vector Length, as an effort to steer programmers towards Silicon-independent assembler. This requires **all** algorithms to contain a loop construct.
+ MAXVL in SVP64 is a Spec-hard-fixed quantity therefore loop constructs are not necessary 100% of the time.
+* (21): like SVP64 it is up to the hardware implementor (Silicon partner) to choose whether to support 128-bit elements.
+* (22): [NEC SX Aurora](https://ftp.libre-soc.org/NEC_SX_Aurora_TSUBASA_VectorEngine-as-manual-v1.2.pdf) is based on the original Cray Vectors
+* (23): [Aurora ISA guide](https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf) Appendix-3 11.1 p508
+* (24): Like the original Cray Vectors, the ISA Vector Length is independent of the underlying hardware, however Generation 1 has 256 elements per Vector register (3.2.4 p24, Aurora ISA guide)
+* (25): If treated as a 1-Dimensional ISA, and designed badly, the 24-bit Prefix expands 200+ scalar instructions to well over a million intrinsics (N~=10^4 **times** M~=10^2).
+ If treated as a 2-Dimensional ISA and designed well, there are far less. N prefix intrinsics **plus** M scalar instruction intrinsics, where N is likely to be of the order of 10^2 and M of the order of 10^2.
+* (26): [Altivec gcc intrinsics](https://gcc.gnu.org/onlinedocs/gcc/PowerPC-AltiVec_002fVSX-Built-in-Functions.html), contains links to additional VSX intrinsics for ISA 2.05/6/7, 3.0 and 3.1
+* (27): NEON 32-bit 2754 intrinsics, NEON 64-bit 4334 intrinsics.
+* (28): SVE: 4140 intrinsics, SVE2 1900 intrinsics
+* (29): Count includes SSE, SSE2, AVX, AVX2 and all AVX512 variants
+* (30): [RVV intrinsics listing](https://raw.githubusercontent.com/riscv-non-isa/rvv-intrinsic-doc/master/intrinsic_funcs.md) page is 25,000 lines long.
+* (31): Unknown. estimated to be of the order of length of RVV due to also being a Cray-style Scalable ISA.