X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=openpower%2Fsv%2Fldst.mdwn;h=ca67a4f004ba1461da6fd59f5613fa0a9168961e;hb=0a873ae35b9633a01c0090a30d919cc8c979cdfc;hp=154c1693b4c35d4dd9734d118e67b840433ea780;hpb=711edbc2b28c3accdf5c1e102de6c762bced4b76;p=libreriscv.git diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index 154c1693b..ca67a4f00 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -9,14 +9,45 @@ Links: * * * +* [[simple_v_extension/specification/ld.x]] + +# Rationale + +All Vector ISAs dating back fifty years have extensive and comprehensive +Load and Store operations that go far beyond the capabilities of Scalar +RISC or CISC processors, yet at their heart on an individual element +basis may be found to be no different from RISC Scalar equivalents. + +The resource savings from Vector LD/ST are significant and stem from +the fact that one single instruction can trigger a dozen (or in some +microarchitectures such as Cray or NEC SX Aurora) hundreds of element-level Memory accesses. + +Additionally, and simply: if the Arithmetic side of an ISA supports +Vector Operations, then in order to keep the ALUs 100% occupied the +Memory infrastructure (and the ISA itself) correspondingly needs Vector +Memory Operations as well. + +Vectorised Load and Store also presents an extra dimension (literally) +which creates scenarios unique to Vector applications, that a Scalar +(and even a SIMD) ISA simply never encounters. SVP64 endeavours to +add such modes without changing the behaviour of the underlying Base +(Scalar) v3.0B operations. + +# Modes overview Vectorisation of Load and Store requires creation, from scalar operations, -a number of different types: +a number of different modes: -* fixed stride (contiguous sequence with no gaps) +* fixed stride (contiguous sequence with no gaps) aka "unit" stride * element strided (sequential but regularly offset, with gaps) * vector indexed (vector of base addresses and vector of offsets) -* fail-first on the same (where it makes sense to do so) +* Speculative fail-first (where it makes sense to do so) +* Structure Packing (covered in SV by [[sv/remap]]). + +Also included in SVP64 LD/ST is both signed and unsigned Saturation, +as well as Element-width overrides and Twin-Predication. + +# Vectorisation of Scalar Power ISA v3.0B OpenPOWER Load/Store operations may be seen from [[isa/fixedload]] and [[isa/fixedstore]] pseudocode to be of the form: @@ -37,12 +68,11 @@ example only the one source and one dest may be marked as scalar or vector. Thus we can see that Vector Indexed may be covered, and, as demonstrated -with the pseudocode below, the immediate can be set to the element width -in order to give unit or element stride. With there being no way to tell which from the Scalar opcode, the choice is provided instead by the SV Context. +with the pseudocode below, the immediate can be used to give unit stride or element stride. With there being no way to tell which from the OpenPOWER v3.0B Scalar opcode alone, the choice is provided instead by the SV Context. # LD not VLD! format - ldop RT, immed(RA) # op_width: lb=1, lh=2, lw=4, ld=8 - op_load(RT, RA, op_width, immed, svctx, RAupdate): + op_load(RT, RA, RC, op_width, immed, svctx, RAupdate):  ps = get_pred_val(FALSE, RA); # predication on src  pd = get_pred_val(FALSE, RT); # ... AND on dest  for (i=0, j=0, u=0; i < VL && j < VL;): @@ -50,14 +80,21 @@ in order to give unit or element stride. With there being no way to tell which if (RA.isvec) while (!(ps & 1<>= 1 + return result + Indexed LD is: # format: ldop RT, RA, RB @@ -92,94 +138,175 @@ Indexed LD is: if (RAupdate.isvec) while (!(ps & 1< + RA,RB RT.v {RA|RB}.v UNDEFINED + RA,RB RT.s {RA|RB}.v UNDEFINED + RA,RB RT.v {RA&RB}.s VSPLAT possible. stride selectable + RA,RB RT.s {RA&RB}.s not vectorised + +Signed Effective Address computation is only relevant for +Vector Indexed Mode, when elwidth overrides are applied. +The source override applies to RB, and before adding to +RA in order to calculate the Effective Address, if SEA is +set RB is sign-extended from elwidth bits to the full 64 +bits. For other Modes (ffirst, saturate), +all EA computation with elwidth overrides is unsigned. + +Note that cache-inhibited LD/ST (`ldcix`) when VSPLAT is activated will perform **multiple** LD/ST operations, sequentially. `ldcix` even with scalar src will read the same memory location *multiple times*, storing the result in successive Vector destination registers. This because the cache-inhibit instructions are used to read and write memory-mapped peripherals. +If a genuine cache-inhibited LD-VSPLAT is required then a *scalar* +cache-inhibited LD should be performed, followed by a VSPLAT-augmented mv. + +## LD/ST ffirst + +LD/ST ffirst treats the first LD/ST in a vector (element 0) as an +ordinary one. Exceptions occur "as normal". However for elements 1 +and above, if an exception would occur, then VL is **truncated** to the +previous element: the exception is **not** then raised because the +LD/ST was effectively speculative. + +ffirst LD/ST to multiple pages via a Vectorised Index base is considered a security risk due to the abuse of probing multiple pages in rapid succession and getting feedback on which pages would fail. Therefore Vector Indexed LD/ST is prohibited entirely, and the Mode bit instead used for element-strided LD/ST. See + + for(i = 0; i < VL; i++) + reg[rt + i] = mem[reg[ra] + i * reg[rb]]; + +High security implementations where any kind of speculative probing +of memory pages is considered a risk should take advantage of the fact that +implementations may truncate VL at any point, without requiring software +to be rewritten and made non-portable. Such implementations may choose +to *always* set VL=1 which will have the effect of terminating any +speculative probing (and also adversely affect performance), but will +at least not require applications to be rewritten. + +Low-performance simpler hardware implementations may +choose (always) to also set VL=1 as the bare minimum compliant implementation of +LD/ST Fail-First. It is however critically important to remember that +the first element LD/ST **MUST** be treated as an ordinary LD/ST, i.e. +**MUST** raise exceptions exactly like an ordinary LD/ST. + +For ffirst LD/STs, VL may be truncated arbitrarily to a nonzero value for any implementation-specific reason. For example: it is perfectly reasonable for implementations to alter VL when ffirst LD or ST operations are initiated on a nonaligned boundary, such that within a loop the subsequent iteration of that loop begins subsequent ffirst LD/ST operations on an aligned boundary +such as the beginning of a cache line, or beginning of a Virtual Memory +page. Likewise, to reduce workloads or balance resources. + +Vertical-First Mode is slightly strange in that only one element +at a time is ever executed anyway. Given that programmers may +legitimately choose to alter srcstep and dststep in non-sequential +order as part of explicit loops, it is neither possible nor +safe to make speculative assumptions about future LD/STs. +Therefore, Fail-First LD/ST in Vertical-First is `UNDEFINED`. +This is very different from Arithmetic (Data-dependent) FFirst +where Vertical-First Mode is deterministic, not speculative. + +# LOAD/STORE Elwidths Loads and Stores are almost unique in that the OpenPOWER Scalar ISA provides a width for the operation (lb, lh, lw, ld). Only `extsb` and @@ -187,7 +314,7 @@ others like it provide an explicit operation width. There are therefore *three* widths involved: * operation width (lb=8, lh=16, lw=32, ld=64) -s src elelent width override +* src elelent width override * destination element width override Some care is therefore needed to express and make clear the transformations, @@ -207,6 +334,17 @@ is treated effectively as completely separate and distinct from SV augmentation. This is primarily down to quirks surrounding LE/BE and byte-reversal in OpenPOWER. +It is unfortunately possible to request an elwidth override on the memory side which +does not mesh with the operation width: these result in `UNDEFINED` +behaviour. The reason is that the effect of attempting a 64-bit `sv.ld` +operation with a source elwidth override of 8/16/32 would result in +overlapping memory requests, particularly on unit and element strided +operations. Thus it is `UNDEFINED` when the elwidth is smaller than +the memory operation width. Examples include `sv.lw/sw=16/els` which +requests (overlapping) 4-byte memory reads offset from +each other at 2-byte intervals. Store likewise is also `UNDEFINED` +where the dest elwidth override is less than the operation width. + Note the following regarding the pseudocode to follow: * `scalar identity behaviour` SV Context parameter conditions turn this @@ -250,7 +388,6 @@ and other modes have all been removed, for clarity and simplicity: if (bytereverse): memread = byteswap(memread, op_width) - # check saturation. if svpctx.saturation_mode: ... saturation adjustment... @@ -287,3 +424,62 @@ min/max Vectorised instructions as post-processing stages. Thus we do not need to provide specialist LD/ST "Structure Packed" opcodes because the generic abstracted concept of "Remapping", when applied to LD/ST, will give that same capability, with far more flexibility. + +# notes from lxo + +this section covers assembly notation for the immediate and indexed LD/ST. +the summary is that in immediate mode for LD it is not clear that if the +destination register is Vectorised `RT.v` but the source `imm(RA)` is scalar +the memory being read is *still a vector load*, known as "unit or element strides". + +This anomaly is made clear with the following notation: + + sv.ld RT.v, imm(RA).v + +The following notation, although technically correct due to being implicitly identical to the above, is prohibited and is a syntax error: + + sv.ld RT.v, imm(RA) + +Notes taken from IRC conversation + + sv.ld r#.v, ofst(r#).v -> the whole vector is at ofst+r# + sv.ld r#.v, ofst(r#.v) -> r# is a vector of addresses + similarly sv.ldx r#.v, r#, r#.v -> whole vector at r#+r# + whereas sv.ldx r#.v, r#.v, r# -> vector of addresses + point being, you take an operand with the "m" constraint (or other memory-operand constraints), append .v to it and you're done addressing the in-memory vector + as in asm ("sv.ld1 %0.v, %1.v" : "=r"(vec_in_reg) : "m"(vec_in_mem)); + (and ld%U1 got mangled into underline; %U expands to x if the address is a sum of registers + +permutations of vector selection, to identify above asm-syntax: + + imm(RA) RT.v RA.v nonstrided + sv.ld r#.v, ofst(r#2.v) -> r#2 is a vector of addresses + mem@ 0+r#2 offs+(r#2+1) offs+(r#2+2) + destreg r# r#+1 r#+2 + imm(RA) RT.s RA.v nonstrided + sv.ld r#, ofst(r#2.v) -> r#2 is a vector of addresses + (dest r# is scalar) -> VSELECT mode + imm(RA) RT.v RA.s fixed stride: unit or element + sv.ld r#.v, ofst(r#2).v -> whole vector is at ofst+r#2 + mem@r#2 +0 +1 +2 + destreg r# r#+1 r#+2 + sv.ld/els r#.v, ofst(r#2).v -> vector at ofst*elidx+r#2 + mem@r#2 +0 ... +offs ... +offs*2 + destreg r# r#+1 r#+2 + imm(RA) RT.s RA.s not vectorised + sv.ld r#, ofst(r#2) + +indexed mode: + + RA,RB RT.v RA.v RB.v + sv.ldx r#.v, r#2, r#3.v -> whole vector at r#2+r#3 + RA,RB RT.v RA.s RB.v + sv.ldx r#.v, r#2.v, r#3.v -> whole vector at r#2+r#3 + RA,RB RT.v RA.v RB.s + sv.ldx r#.v, r#2.v, r#3 -> vector of addresses + RA,RB RT.v RA.s RB.s + sv.ldx r#.v, r#2, r#3 -> VSPLAT mode + RA,RB RT.s RA.v RB.v + RA,RB RT.s RA.s RB.v + RA,RB RT.s RA.v RB.s + RA,RB RT.s RA.s RB.s not vectorised