X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=openpower%2Fsv%2Foverview.mdwn;h=28fc21b98291ad67eab605c1ec8ae4d663b316a4;hb=0f9ec84b2dd34f91accc08570febec11b6ead781;hp=d92a3722712449ad0b30f4ccaf9fb9b8869022da;hpb=24c4a87f925acdef08c8377853bf03e5dc8b18fc;p=libreriscv.git

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index d92a37227..28fc21b98 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -39,10 +39,11 @@ registers from 32 to 64 bit).
 
 The fundamentals are:
 
-* The Program Counter gains a "Sub Counter" context.
-* Vectorisation pauses the PC and runs a loop from 0 to VL-1
- (where VL is Vector Length). This may be thought of as a
-   "Sub-PC"
+* The Program Counter (PC) gains a "Sub Counter" context (Sub-PC)
+* Vectorisation pauses the PC and runs a Sub-PC loop from 0 to VL-1
+  (where VL is Vector Length)
+* The Program Order of "Sub-PC" instructions must be preserved,
+  just as is expected of instructions ordered by the PC.
 * Some registers may be "tagged" as Vectors
 * During the loop, "Vector"-tagged register are incremented by
   one with each iteration, executing the *same instruction*