X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=openpower%2Fsv%2Frfc%2Fls011.mdwn;h=2ad57716771c66f25274958c5ba46905158a058a;hb=fc2a6d3269771ffeeb423b4b0d9f6928a318b5c1;hp=4cb05c3e9d4b11bdf3eb764ce4e8d94c59c75f7f;hpb=7029dab0d1647fac0834a9ee6c66e872ed2010db;p=libreriscv.git diff --git a/openpower/sv/rfc/ls011.mdwn b/openpower/sv/rfc/ls011.mdwn index 4cb05c3e9..2ad577167 100644 --- a/openpower/sv/rfc/ls011.mdwn +++ b/openpower/sv/rfc/ls011.mdwn @@ -1,13 +1,68 @@ -# LD/ST-Update-PostIncrement - -TODO (key stub notes below) +# RFC ls011 LD/ST-Update-PostIncrement +* Funded by NLnet under the Privacy and Enhanced Trust Programme, EU + Horizon2020 Grant 825310, and NGI0 Entrust No 101069594 * +* +* +* + +**Severity**: Major + +**Status**: New + +**Date**: 21 Apr 2023. -The following instructions are proposed to be added in EXT2xx, -duplicating LD/ST-Update functionality but moving the update -of RA to *after* the Memory operation. These types of -instructions are already present in x86 (sort-of). +**Target**: v3.2B + +**Source**: v3.0B + +**Books and Section affected**: + +``` + Chapter 2 Book I, new Fixed-Point Load / Store Sections 3.3.2 3.3.3 + Chapter 4 Book I, new Floating-Point Load / Store Sections 4.6.2 4.6.3 +``` + +**Summary** + +``` + TODO +``` + +**Submitter**: Luke Leighton (Libre-SOC) + +**Requester**: Libre-SOC + +**Impact on processor**: + +``` + Addition of new Load/Store Fixed and Floating Point instructions +``` + +**Impact on software**: + +``` + Requires support for new instructions in assembler, debuggers, and related tools. + Reduces instructions in hot-loops +``` + +**Keywords**: + +``` + +``` + +**Motivation** + +Moving the update of RA to *after* the Memory operation saves on instruction count +both outside and inside hot-loops. strncpy may be reduced to 11 Vector instructions, +3 of which are the zeroing loop, 5 of which are the copy. Percentage-wise LD/ST +Update Post-Increment represents a massive 20% reduction. + +**Notes and Observations**: + +These types of instructions are already present in x86 (sort-of). * x86 chose that store should be pre-indexed and load should be post-indexed * Power ISA chose everything to be pre-indexed @@ -17,6 +72,23 @@ instructions are already present in x86 (sort-of). +**Changes** + +Add the following entries to: + +* New Load/Store Sections +* Appendices + +[[!tag opf_rfc]] + +-------- + +\newpage{} + +TODO (key stub notes below) + + + The LD/ST-Immediate-Post-Increment instructions are all Primary Opcode: there are 13 of these. LD/ST-Indexed-Post-Increment are all effectively 9-bit XO and consequently may easily @@ -52,26 +124,26 @@ stdup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W stdupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W # FP LD/ST-Postincrement -lfdu, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W -lfsu, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W -lfdux, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W -lsdux, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W -stfdu, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W -stfsu, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W -stfdux, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W -stfsux, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W +lfdup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W +lfsup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedload, 1R2W +lfdupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W +lsdupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedload, 2R2W +stfdup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W +stfsup, ls011, high, PO, yes, EXT2xx, no, isa/pifixedstore, 2R1W +stfdupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W +stfsupx, ls011, high, 10, yes, EXT2xx, no, isa/pifixedstore, 3R1W # LD/ST-Shifted-Postincrement -lbzuspx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W -lhzuspx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W -lhauspx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W -lwzuspx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W -lwauspx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W -lduspx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W -stbuspx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W -sthuspx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W -stwuspx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W -stduspx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W +lbzupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W +lhzupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W +lhaupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W +lwzupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W +lwaupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W +ldupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W +stbupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W +sthupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W +stwupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W +stdupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 3R1W # FP LD/ST-Shifted-Postincrement lfdupsx, ls011, med, 10, yes, EXT2xx, no, ls011, 2R2W @@ -88,7 +160,7 @@ just use `RA` as the address, otherwise remaining the same. No actual change to the Effective Address computation itself occurs, in any of the Post-Update instructions. -** Load Byte and Zero with Post-Update** +**Load Byte and Zero with Post-Update** D-Form @@ -121,186 +193,63 @@ where the same pseudocode for `lbzu` is: # Fixed-point Load with Post-Update -Add the following additional Section to Fixed-Point Load Book I +Add the following additional Section to Fixed-Point Load: Book I 3.3.2.1 -## Load Byte and Zero with Post-Update - -D-Form - -* lbzup RT,D(RA) - -Pseudo-code: - - EA <- (RA) - RT <- ([0] * (XLEN-8)) || MEM(EA, 1) - RA <- (RA) + EXTS(D) - -Special Registers Altered: - - None +[[!inline pages="openpower/isa/pifixedload" raw=yes ]] -## Load Byte and Zero with Post-Update Indexed - -X-Form - -* lbzupx RT,RA,RB - -Pseudo-code: - - EA <- (RA) - RT <- ([0] * (XLEN-8)) || MEM(EA, 1) - RA <- (RA) + (RB) - -Special Registers Altered: - - None - -## Load Halfword and Zero with Post-Update - -D-Form - -* lhzup RT,D(RA) - -Pseudo-code: - - EA <- (RA) - RT <- ([0] * (XLEN-16)) || MEM(EA, 2) - RA <- (RA) + EXTS(D) - -Special Registers Altered: - - None - -## Load Halfword and Zero with Post-Update Indexed - -X-Form - -* lhzupx RT,RA,RB - -Pseudo-code: - - EA <- (RA) - RT <- ([0] * (XLEN-16)) || MEM(EA, 2) - RA <- (RA) + (RB) - -Special Registers Altered: - - None - -## Load Halfword Algebraic with Post-Update - -D-Form - -* lhaup RT,D(RA) - -Pseudo-code: - - EA <- (RA) - RT <- EXTS(MEM(EA, 2)) - RA <- (RA) + EXTS(D) - -Special Registers Altered: - - None - -## Load Halfword Algebraic with Post-Update Indexed - -X-Form - -* lhaupx RT,RA,RB - -Pseudo-code: - - EA <- (RA) - RT <- EXTS(MEM(EA, 2)) - RA <- (RA) + (RB) - -Special Registers Altered: - - None - -## Load Word and Zero with Post-Update - -D-Form - -* lwzup RT,D(RA) - -Pseudo-code: - - EA <- (RA) - RT <- [0]*32 || MEM(EA, 4) - RA <- (RA) + EXTS(D) - -Special Registers Altered: - - None - -## Load Word and Zero with Post-Update Indexed - -X-Form - -* lwzupx RT,RA,RB - -Pseudo-code: - - EA <- (RA) - RT <- [0] * 32 || MEM(EA, 4) - RA <- (RA) + (RB) +----- -Special Registers Altered: +\newpage{} - None +# Fixed-Point Store Post-Update -## Load Word Algebraic with Post-Update Indexed +Add the following as a new section in Fixed-Point Store, Book I -X-Form +[[!inline pages="openpower/isa/pifixedstore" raw=yes ]] -* lwaupx RT,RA,RB +----- -Pseudo-code: +\newpage{} - EA <- (RA) - RT <- EXTS(MEM(EA, 4)) - RA <- (RA) + (RB) +# Floating-Point Load Post-Update -Special Registers Altered: +Add the following as a new section in Floating-Point Load, Book I 4.6.2 - None +[[!inline pages="openpower/isa/fpload" raw=yes ]] -## Load Doubleword with Post-Update Indexed +----- -DS-Form +\newpage{} -* ldup RT,DS(RA) +# Floating-Point Store Post-Update -Pseudo-code: +Add the following as a new section in Floating-Point Store, Book I 4.6.3 - EA <- (RA) - RT <- MEM(EA, 8) - RA <- (RA) + EXTS(DS || 0b00) +[[!inline pages="openpower/isa/fpstore" raw=yes ]] -Special Registers Altered: +----- - None +\newpage{} -## Load Doubleword with Post-Update Indexed +# Fixed-Point Load Shifted Post-Update -X-Form +Add the following as a new section in Fixed-Point Load: Book I -* ldupx RT,RA,RB +[[!inline pages="openpower/isa/pifixedloadshift" raw=yes ]] -Pseudo-code: +----- - EA <- (RA) - RT <- MEM(EA, 8) - RA <- (RA) + (RB) +\newpage{} -Special Registers Altered: +# Fixed-Point Store Shifted Post-Update - None +Add the following as a new section in Fixed-Point Store: Book I ------ +[[!inline pages="openpower/isa/pifixedstoreshift" raw=yes ]] \newpage{} +[[!inline pages="openpower/isa/fixedload" raw=yes ]] +\newpage{} +[[!inline pages="openpower/isa/fixedstore" raw=yes ]] [[!tag opf_rfc]]