X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=openpower%2Fsv%2Frfc%2Fls011.mdwn;h=fc13abc544a822c1eabd3515b04119a029f47aa5;hb=af645794cab13e73fa5e1f0cada344342584a00d;hp=54559914c7304619eb68a3a25620f581b89fffab;hpb=fd9166f08b1f79f7aaa672ba95943ac6372fdaaf;p=libreriscv.git diff --git a/openpower/sv/rfc/ls011.mdwn b/openpower/sv/rfc/ls011.mdwn index 54559914c..fc13abc54 100644 --- a/openpower/sv/rfc/ls011.mdwn +++ b/openpower/sv/rfc/ls011.mdwn @@ -195,301 +195,7 @@ where the same pseudocode for `lbzu` is: Add the following additional Section to Fixed-Point Load: Book I 3.3.2.1 -## Load Byte and Zero with Post-Update - -D-Form - -``` - |0 |6 |9 |10 |11 |16 |31 | - | PO | RT | RA| D | -``` - -* lbzup RT,D(RA) - -Pseudo-code: - -``` - EA <- (RA) - RT <- ([0] * (XLEN-8)) || MEM(EA, 1) - RA <- (RA) + EXTS(D) -``` - -Let the effective address (EA) be (RA|0). -The byte in storage addressed by EA is loaded into -RT[56:63]. RT[0:55] are set to 0. - -The sum (RA|0)+D is placed into register RA. - -If RA=0 or RA=RT, the instruction form is invalid. - -Special Registers Altered: - - None - -## Load Byte and Zero with Post-Update Indexed - -X-Form - -``` - |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 | - | PO | RT | RA | RB | XO | / | -``` - -* lbzupx RT,RA,RB - -Pseudo-code: - -``` - EA <- (RA) - RT <- ([0] * (XLEN-8)) || MEM(EA, 1) - RA <- (RA) + (RB) -``` - -Let the effective address (EA) be (RA). -The byte in storage addressed by EA is loaded into -RT[56:63]. RT[0:55] are set to 0. - -The sum (RA)+(RB) is placed into register RA. - -If RA=0 or RA=RT, the instruction form is invalid. - -Special Registers Altered: - - None - -## Load Halfword and Zero with Post-Update - -D-Form - -``` - |0 |6 |9 |10 |11 |16 |31 | - | PO | RT | RA| D | -``` - -* lhzup RT,D(RA) - -Pseudo-code: - -``` - EA <- (RA) - RT <- ([0] * (XLEN-16)) || MEM(EA, 2) - RA <- (RA) + EXTS(D) -``` - -Let the effective address (EA) be (RA|0). -The halfword in storage addressed by EA is loaded into -RT[48:63]. RT[0:47] are set to 0. - -The sum (RA|0)+D is placed into register RA. - -If RA=0 or RA=RT, the instruction form is invalid. - -Special Registers Altered: - - None - -## Load Halfword and Zero with Post-Update Indexed - -X-Form - -``` - |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 | - | PO | RT | RA | RB | XO | / | -``` - -* lhzupx RT,RA,RB - -Pseudo-code: - -``` - EA <- (RA) - RT <- ([0] * (XLEN-16)) || MEM(EA, 2) - RA <- (RA) + (RB) -``` - -Let the effective address (EA) be (RA). -The halfword in storage addressed by EA is loaded into -RT[48:63]. RT[0:47] are set to 0. - -The sum (RA)+(RB) is placed into register RA. - -If RA=0 or RA=RT, the instruction form is invalid. - -Special Registers Altered: - - None - -## Load Halfword Algebraic with Post-Update - -D-Form - -``` - |0 |6 |9 |10 |11 |16 |31 | - | PO | RT | RA| D | -``` - -* lhaup RT,D(RA) - -Pseudo-code: - -``` - EA <- (RA) - RT <- EXTS(MEM(EA, 2)) - RA <- (RA) + EXTS(D) -``` - -Special Registers Altered: - - None - -## Load Halfword Algebraic with Post-Update Indexed - -X-Form - -``` - |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 | - | PO | RT | RA | RB | XO | / | -``` - -* lhaupx RT,RA,RB - -Pseudo-code: - -``` - EA <- (RA) - RT <- EXTS(MEM(EA, 2)) - RA <- (RA) + (RB) -``` - -Special Registers Altered: - - None - -## Load Word and Zero with Post-Update - -D-Form - -``` - |0 |6 |9 |10 |11 |16 |31 | - | PO | RT | RA| D | -``` - -* lwzup RT,D(RA) - -Pseudo-code: - -``` - EA <- (RA) - RT <- [0]*32 || MEM(EA, 4) - RA <- (RA) + EXTS(D) -``` - -Let the effective address (EA) be (RA|0). -The word in storage addressed by EA is loaded into -RT[32:63]. RT[0:31] are set to 0. - -The sum (RA|0)+D is placed into register RA. - -If RA=0 or RA=RT, the instruction form is invalid. - -Special Registers Altered: - - None - -## Load Word and Zero with Post-Update Indexed - -X-Form - -``` - |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 | - | PO | RT | RA | RB | XO | / | -``` - -* lwzupx RT,RA,RB - -Pseudo-code: - -``` - EA <- (RA) - RT <- [0] * 32 || MEM(EA, 4) - RA <- (RA) + (RB) -``` - -Let the effective address (EA) be (RA). -The word in storage addressed by EA is loaded into -RT[32:63]. RT[0:31] are set to 0. - -The sum (RA)+(RB) is placed into register RA. - -If RA=0 or RA=RT, the instruction form is invalid. - -Special Registers Altered: - - None - -## Load Word Algebraic with Post-Update Indexed - -X-Form - -``` - |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 | - | PO | RT | RA | RB | XO | / | -``` - -* lwaupx RT,RA,RB - -Pseudo-code: - -``` - EA <- (RA) - RT <- EXTS(MEM(EA, 4)) - RA <- (RA) + (RB) -``` - -Special Registers Altered: - - None - -## Load Doubleword with Post-Update Indexed - -DS-Form - -* ldup RT,DS(RA) - -Pseudo-code: - -``` - EA <- (RA) - RT <- MEM(EA, 8) - RA <- (RA) + EXTS(DS || 0b00) -``` - -Special Registers Altered: - - None - -## Load Doubleword with Post-Update Indexed - -X-Form - -``` - |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 | - | PO | RT | RA | RB | XO | / | -``` - -* ldupx RT,RA,RB - -Pseudo-code: - -``` - EA <- (RA) - RT <- MEM(EA, 8) - RA <- (RA) + (RB) -``` - -Special Registers Altered: - - None +[[!inline pages="openpower/isa/pifixedload" raw=yes ]] ----- @@ -499,191 +205,15 @@ Special Registers Altered: Add the following as a new section in Fixed-Point Store, Book I -## Store Byte with Update - -D-Form - -``` - |0 |6 |9 |10 |11 |16 |31 | - | PO | RT | RA| D | -``` - -* stbup RS,D(RA) - -Pseudo-code: - -``` - EA <- (RA) + EXTS(D) - ea <- (RA) - MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1] - RA <- EA -``` - -Special Registers Altered: - - None - -## Store Byte with Update Indexed - -X-Form - -``` - |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 | - | PO | RS | RA | RB | XO | / | -``` - -* stbupx RS,RA,RB - -Pseudo-code: - -``` - EA <- (RA) + (RB) - ea <- (RA) - MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1] - RA <- EA -``` - -Special Registers Altered: - - None - -## Store Halfword with Update - -D-Form - -``` - |0 |6 |9 |10 |11 |16 |31 | - | PO | RT | RA| D | -``` - -* sthup RS,D(RA) - -Pseudo-code: - -``` - EA <- (RA) + EXTS(D) - ea <- (RA) - MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1] - RA <- EA -``` - -Special Registers Altered: - - None +[[!inline pages="openpower/isa/pifixedstore" raw=yes ]] -## Store Halfword with Update Indexed - -X-Form - -``` - |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 | - | PO | RS | RA | RB | XO | / | -``` - -* sthupx RS,RA,RB - -Pseudo-code: - -``` - EA <- (RA) + (RB) - ea <- (RA) - MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1] - RA <- EA -``` - -Special Registers Altered: - - None - -## Store Word with Update - -D-Form - -``` - |0 |6 |9 |10 |11 |16 |31 | - | PO | RT | RA| D | -``` - -* stwup RS,D(RA) - -Pseudo-code: - -``` - EA <- (RA) + EXTS(D) - ea <- (RA) - MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1] - RA <- EA -``` - -Special Registers Altered: - - None - -## Store Word with Update Indexed - -X-Form - -``` - |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 | - | PO | RS | RA | RB | XO | / | -``` - -* stwupx RS,RA,RB - -Pseudo-code: - -``` - EA <- (RA) + (RB) - ea <- (RA) - MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1] - RA <- EA -``` - -Special Registers Altered: - - None - -## Store Doubleword with Update - -DS-Form - -* stdup RS,DS(RA) - -Pseudo-code: - -``` - EA <- (RA) + EXTS(DS || 0b00) - ea <- (RA) - MEM(ea, 8) <- (RS) - RA <- EA -``` - -Special Registers Altered: - - None - -## Store Doubleword with Update Indexed - -X-Form - -``` - |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 | - | PO | RS | RA | RB | XO | / | -``` - -* stdupx RS,RA,RB - -Pseudo-code: - -``` - EA <- (RA) + (RB) - ea <- (RA) - MEM(ea, 8) <- (RS) - RA <- EA -``` - -Special Registers Altered: - - None +\newpage{} +[[!inline pages="openpower/isa/fixedload" raw=yes ]] +\newpage{} +[[!inline pages="openpower/isa/fixedstore" raw=yes ]] +\newpage{} +[[!inline pages="openpower/isa/fpload" raw=yes ]] +\newpage{} +[[!inline pages="openpower/isa/fpstore" raw=yes ]] [[!tag opf_rfc]]