X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=openpower.mdwn;h=259b46e03a927c63957af0ff58f0bbeb437b0a47;hb=1025526907b21d19c29aa79ee7cfc0ef75cb0db7;hp=4c319dde5145d85ca582ede00e0b38c092ba789f;hpb=acf26c23f766ef2da5f1a90896d7f7090abe6214;p=libreriscv.git
diff --git a/openpower.mdwn b/openpower.mdwn
index 4c319dde5..259b46e03 100644
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -4,8 +4,15 @@ EULA released! looks good.
Links
+* OpenPOWER Membership
+
* OpenPower HDL Mailing list
* [[openpower/isatables]]
+* [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
+* [[openpower/gem5]]
+* [[openpower/sv]]
+* [[openpower/pearpc]]
+* [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
* [[3d_gpu/architecture/decoder]]
*
*
@@ -14,6 +21,11 @@ Links
*
*
+PowerPC Unit Tests
+
+*
+*
+
Summary
* FP32 is converted to FP64. Requires SimpleV to be active.
@@ -22,14 +34,14 @@ Summary
* FCVT between 16/32/64 needed
* c++11 atomics not very efficient
* no 16/48/64 opcodes, needs a shuffle of opcodes. TODO investigate Power VLE
-* needs escape sequencing (ISAMUX/NS)
+* needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]]
# What we are *NOT* doing:
* A processor that is fundamentally incompatible (noncompliant) with Power.
(**escape-sequencing requires and guarantees compatibility**).
* Opcode 4 Signal Processing (SPE)
-* Opcode 4 Vectors or Opcode 60 VSX
+* Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
* Avoidable legacy opcodes
# SimpleV
@@ -108,6 +120,28 @@ entire row, 2 bits instead of 3. greatly simplifies decoder.
* OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
* OP 000-110 and 000-111 for VBLOCK. 11 bits available.
+Note that this requires BE instruction encoding (separate from
+data BE/LE encoding). BE encoding always places the major opcode in
+the first 2 bytes of the raw (uninterpreted) sequential instruction
+byte stream.
+
+Thus in BE-instruction-mode, the first 2 bytes may be analysed to
+detect whether the instruction is 16-bit Compressed, 48-bit SVP-P48,
+64-bit SVP-64, variable-length VBLOCK, or plain 32-bit.
+
+It is not possible to distinguish LE-encoded 32-bit instructions
+from LE-encoded 16-bit instructions because in LE-encoded 32-bit
+instructions, the opcode falls into:
+
+* bytes 2 and 3 of any given raw (uninterpreted) sequential instruction
+ byte stream for a 32-bit instruction
+* bytes 0 and 1 for a 16-bit Compressed instruction
+* bytes 4 and 5 for a 48-bit SVP P48
+* bytes 6 and 7 for a 64-bit SVP P64
+
+Clearly this is an impossible situation, therefore BE is the only
+option. Note: *this is completely separate from BE/LE for data*
+
# Compressed 16
Further "escape-sequencing".
@@ -135,7 +169,7 @@ Requirements are to have one instruction in each subpage which resets all the wa
Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
the exception entry point:
-https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
+
the rest of the context switch code is in a different file:
-https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589
+