X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=openpower.mdwn;h=259b46e03a927c63957af0ff58f0bbeb437b0a47;hb=1025526907b21d19c29aa79ee7cfc0ef75cb0db7;hp=a580db6c72d2e406b43ec0cafcc06c962b0449d5;hpb=466c5a1a3e8e25a2e1ac687cd7f697654d0508b5;p=libreriscv.git
diff --git a/openpower.mdwn b/openpower.mdwn
index a580db6c7..259b46e03 100644
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -4,13 +4,27 @@ EULA released! looks good.
Links
+* OpenPOWER Membership
+
+* OpenPower HDL Mailing list
* [[openpower/isatables]]
-* https://forums.raptorcs.com/
-* http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev
-* http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo
-* http://bugs.libre-riscv.org/show_bug.cgi?id=179
-* https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0
-* https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b
+* [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
+* [[openpower/gem5]]
+* [[openpower/sv]]
+* [[openpower/pearpc]]
+* [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
+* [[3d_gpu/architecture/decoder]]
+*
+*
+*
+*
+*
+*
+
+PowerPC Unit Tests
+
+*
+*
Summary
@@ -20,13 +34,14 @@ Summary
* FCVT between 16/32/64 needed
* c++11 atomics not very efficient
* no 16/48/64 opcodes, needs a shuffle of opcodes. TODO investigate Power VLE
-* needs escape sequencing (ISAMUX/NS)
+* needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]]
# What we are *NOT* doing:
* A processor that is fundamentally incompatible (noncompliant) with Power.
+ (**escape-sequencing requires and guarantees compatibility**).
* Opcode 4 Signal Processing (SPE)
-* Opcode 4 Vectors
+* Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
* Avoidable legacy opcodes
# SimpleV
@@ -42,6 +57,14 @@ Thus it is completely unnecessary to add any vector opcodes - at all -
saving hugely on both hardware and compiler development time when
the concept is dropped on top of a pre-existing ISA.
+## Condition Registers
+
+Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1. When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
+
+## Carry
+
+SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits.
+
# Integer Overflow / Saturate
Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE). To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
@@ -97,6 +120,28 @@ entire row, 2 bits instead of 3. greatly simplifies decoder.
* OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
* OP 000-110 and 000-111 for VBLOCK. 11 bits available.
+Note that this requires BE instruction encoding (separate from
+data BE/LE encoding). BE encoding always places the major opcode in
+the first 2 bytes of the raw (uninterpreted) sequential instruction
+byte stream.
+
+Thus in BE-instruction-mode, the first 2 bytes may be analysed to
+detect whether the instruction is 16-bit Compressed, 48-bit SVP-P48,
+64-bit SVP-64, variable-length VBLOCK, or plain 32-bit.
+
+It is not possible to distinguish LE-encoded 32-bit instructions
+from LE-encoded 16-bit instructions because in LE-encoded 32-bit
+instructions, the opcode falls into:
+
+* bytes 2 and 3 of any given raw (uninterpreted) sequential instruction
+ byte stream for a 32-bit instruction
+* bytes 0 and 1 for a 16-bit Compressed instruction
+* bytes 4 and 5 for a 48-bit SVP P48
+* bytes 6 and 7 for a 64-bit SVP P64
+
+Clearly this is an impossible situation, therefore BE is the only
+option. Note: *this is completely separate from BE/LE for data*
+
# Compressed 16
Further "escape-sequencing".
@@ -124,7 +169,7 @@ Requirements are to have one instruction in each subpage which resets all the wa
Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
the exception entry point:
-https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
+
the rest of the context switch code is in a different file:
-https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589
+