X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=openpower.mdwn;h=5e534f619e4b55f7659b12415aa080d6479dc827;hb=a0aa0fa04e2de4c74dc920af2eccd7dc9754889f;hp=7dd5cc70ead9724485b330dbb273c250f5b1762f;hpb=067b521ca521e825350885c0e19659bc3d945f88;p=libreriscv.git

diff --git a/openpower.mdwn b/openpower.mdwn
index 7dd5cc70e..5e534f619 100644
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -9,6 +9,7 @@ Links
 * [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
 * [[openpower/gem5]]
 * [[openpower/pearpc]]
+* [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
 * [[3d_gpu/architecture/decoder]]
 * <https://forums.raptorcs.com/>
 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
@@ -30,14 +31,14 @@ Summary
 * FCVT between 16/32/64 needed
 * c++11 atomics not very efficient
 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
-* needs escape sequencing (ISAMUX/NS)
+* needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]]
 
 # What we are *NOT* doing:
 
 * A processor that is fundamentally incompatible (noncompliant) with Power.
  (**escape-sequencing requires and guarantees compatibility**).
 * Opcode 4 Signal Processing (SPE)
-* Opcode 4 Vectors or Opcode 60 VSX
+* Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
 * Avoidable legacy opcodes
 
 # SimpleV