X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=openpower.mdwn;h=da186f35b69cb6ad4c6d427ea795e555f6f0888e;hb=94d4c6c37dd8d5faa1e1bda62e2ddfbcb5f16af1;hp=d7d2dbfa7f0f104b89c9451eb66b39780467fafd;hpb=11a8c723e5d9d75762a68fa57179aa932bfb7917;p=libreriscv.git diff --git a/openpower.mdwn b/openpower.mdwn index d7d2dbfa7..da186f35b 100644 --- a/openpower.mdwn +++ b/openpower.mdwn @@ -1,16 +1,37 @@ +# OpenPOWER + +In the late 1980s [[!wikipedia IBM]] developed a POWER family of processors. +This evolved to a specification known as the POWER ISA. In 2019 IBM made the POWER ISA [[!wikipedia Open_source]], to be looked after by the existing [[!wikipedia OpenPOWER_Foundation]]. Here is a longer history of [[!wikipedia IBM_POWER_microprocessors]]. These IBM proprietary processors +happen to implement what is now known as the POWER ISA. The names +POWER8, POWER9, POWER10 etc. are product designations equivalent to Intel +i5, i7, i9 etc. and are frequently conflated with versions of the POWER ISA (v2.07, v3.0c, v3.1b). + +Libre-SOC is basing its [[Simple-V Vectorisation|sv]] CPU extensions on POWER ISA, because it wants to be able to specify a machine that can be completely trusted, and because POWER, thanks to IBM's involvement, +is designed for high performance. + +See wikipedia page + + +very useful resource describing all assembly instructions + + # Evaluation EULA released! looks good. + -Links +# Links * OpenPOWER Membership - + * OpenPower HDL Mailing list * [[openpower/isatables]] +* [[openpower/whitepapers]] * [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec * [[openpower/gem5]] * [[openpower/sv]] +* [[openpower/prefix_codes]] Decode/encode prefix-codes, used by JPEG, DEFLATE, etc. +* [[openpower/opcode_regs_deduped]] * [[openpower/simd_vsx]] * [[openpower/ISA_WG]] - OpenPOWER ISA Working Group * [[openpower/pearpc]] @@ -45,10 +66,11 @@ Summary * Opcode 4 Signal Processing (SPE) * Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions) * Avoidable legacy opcodes +* SIMD. it's awful. # SimpleV -see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below. +see [[openpower/sv]]. SimpleV: a "hardware for-loop" which involves type-casting (both) the register files to "a sequence of elements". The **one** instruction (an unmodified **scalar** instruction) is interpreted as a *hardware @@ -59,14 +81,6 @@ Thus it is completely unnecessary to add any vector opcodes - at all - saving hugely on both hardware and compiler development time when the concept is dropped on top of a pre-existing ISA. -## Condition Registers - -Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1. When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead. - -## Carry - -SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits. - # Integer Overflow / Saturate Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE). To be done instead as CSRs / vector-flags on *standard* arithmetic operations. @@ -166,12 +180,3 @@ Store activation length in a CSR. Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1". -# RISCV userspace - -Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs. - -the exception entry point: - - -the rest of the context switch code is in a different file: -